S1D13700F01A100 Epson, S1D13700F01A100 Datasheet - Page 219

• Manufacturer Part Number: S1D13700F01A100
• Description: Display Drivers LCD CONTROLLER
• Manufacturer: Epson

Specifications of S1D13700F01A100

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

3: INTERFACING TO THE MOTOROLA MCF5307 “COLDFIRE” MICROPROCESSOR
3 I
3.1 Introduction
3.2 Interfacing to the MCF5307
The MCF5307 System Bus
Overview
Normal (Non-Burst) Bus Transactions
5-18
MCF5307 “C
This application note describes the hardware required to interface the S1D13705 Embedded
Memory LCD Controller and the Motorola MCF5307 Processor. The pairing of these two devices
results in an embedded system offering impressive display capability with very low power
consumption.
The MCF5200/5300 family of processors feature a high-speed synchronous system bus typical of
modern microprocessors. This section is an overview of the operation of the CPU bus to establish
interface requirements.
The MCF5307 microprocessor family uses a synchronous address and data bus, very similar in
architecture to the MC68040 and MPC8xx. All outputs and inputs are timed with respect to a
square-wave reference clock called BCLK0 (Master Clock). This clock runs at a software-selectable
divisor rate from the machine cycle speed of the CPU core, typically 20 to 33 MHz. Both the address
and the data bus are 32 bits in width. All IO accesses are memory-mapped; there is no separate IO
space in the Coldfire architecture.
The bus can support two types of cycles, normal and burst. Burst memory cycles are used to fill on-
chip cache memories, and for certain on-chip DMA operations. Normal cycles are used for all other
data transfers.
A data transfer is initiated by the bus master by placing the memory address on address lines A31
through A0 and driving TS (Transfer Start) low for one clock cycle. Several control signals are also
provided with the memory address:
• SIZ[1:0] (Transfer Size), which indicate whether the bus cycle is 8, 16, or 32 bits in width.
• R/W, which is high for read cycles and low for write cycles.
• A set of transfer type signals (TT[1:0]) which provide more detail on the type of transfer being
• TIP (Transfer In Progress), which is asserted whenever a bus cycle is active.
When the peripheral device being accessed has completed the bus transfer, it asserts TA (Transfer
Acknowledge) for one clock cycle, completing the bus transaction. Once TA has been asserted, the
MCF5307 will not start another bus cycle until TA has been de-asserted. The minimum length of a
bus transaction is two bus clocks.
X27A-G-011-01
attempted.
NTERFACING TO THE
OLD
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EPSON
IRE
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” M
OTOROLA
ICROPROCESSOR
S1D13705F00A APPLICATION NOTES
(X27A-G-011-01)