S1D13700F01A100 Epson, S1D13700F01A100 Datasheet - Page 248

• Manufacturer Part Number: S1D13700F01A100
• Description: Display Drivers LCD CONTROLLER
• Manufacturer: Epson

Specifications of S1D13700F01A100

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

7.4 VR4102/VR4111 to S1D13705 Interface
Hardware Description
S1D13705F00A APPLICATION NOTES
(X27A-G-008-01)
NEC VR4102/VR4111
Note:
When connecting the S1D13705 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
• WAIT# is a signal which is output from the S1D13705 to the host CPU that indicates when data is
• The Bus Status (BS#) and Read/Write (RD/WR#) signals are not used in the bus interface for
The NEC VR4102/VR4111 Microprocessor is specifically designed to support an external LCD
controller by providing the internal address decoding and control signals necessary. By using the
Generic # 2 interface, no glue logic is required to interface the S1D13705 and the NEC VR4102/
VR4111. A pull-up resistor is attached to WAIT# to speed up its rise time when terminating a cycle.
The following diagram shows a typical implementation of the VR4102/VR4111 to S1D13705
interface.
ready (read cycle) or accepted (write cycle) on the host bus. Since host CPU accesses to the
S1D13705 may occur asynchronously to the display update, it is possible that contention may
occur in accessing the S1D13705 internal registers and/or refresh memory. The WAIT# line
resolves these contentions by forcing the host to wait until the resource arbitration is complete.
This signal is active low and may need to be inverted if the host CPU wait state signal is active
high.
Generic #2 mode. However, BS# is used to configure the S1D13705 for Generic #2 mode and
should be tied high (connected to IO V
DATA[15:0]
ADD[16:0]
LCDRDY
BUSCLK
LCDCS#
SHB#
WR#
RD#
Figure 7-2 Typical Implementation of VR4102/VR4111 to S1D13705 Interface
7: INTERFACING TO THE NEC VR4102/VR4111 MICROPROCESSOR
DD
EPSON
). RD/WR# should also be tied high.
Pull-up
System RESET
Vcc
Vcc
RD#
WE1#
RD/WR#
CS#
WAIT#
RESET#
AB[16:0]
DB[15:0]
BUSCLK
BS#
WE0#
S1D13705
5-47