S1D13700F01A100 Epson, S1D13700F01A100 Datasheet - Page 239

• Manufacturer Part Number: S1D13700F01A100
• Description: Display Drivers LCD CONTROLLER
• Manufacturer: Epson

Specifications of S1D13700F01A100

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

6: INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR
Generic #2 Interface Mode
5-38
Generic #2 interface mode is a general and non-processor-specific interface mode on the S1D13705.
The Generic # 2 interface mode was chosen for this interface due to the simplicity of its timing and
compatibility with the PR31500/PR31700 control signals.
The interface requires the following signals:
• BUSCLK is a clock input which synchronizes transfers between the host CPU and the S1D13705.
• The address inputs AB0 through AB16, and the data bus DB0 through DB15, connect directly to
• Chip Select (CS#) is driven by decoding the high-order address lines to select the proper register
• WE1# is the high byte enable for both read and write cycles.
• WE0# is the write enable signal for the S1D13705, to be driven low when the host CPU is writing
• RD# is the read enable for the S1D13705, to be driven low when the host CPU is reading data
• WAIT# is a signal which is output from the S1D13705 to the host CPU that indicates when data is
• The Bus Status (BS#) and Read/Write (RD/WR#) signals are not used in the bus interface for
It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock.
the CPU address and data bus, respectively. On 32-bit big endian architectures such as the Power
PC, the data bus would connect to the high-order data lines; on little endian hosts, or 16-bit big
endian hosts, they would connect to the low-order data lines. The hardware engineer must ensure
that CNF3 selects the proper endian mode upon reset.
and memory address space.
data from the S1D13705.
from the S1D13705.
ready (read cycle) or accepted (write cycle) on the host bus. Since host CPU accesses to the
S1D13705 may occur asynchronously to the display update, it is possible that contention may
occur in accessing the 13705 internal registers and/or refresh memory. The WAIT# line resolves
these contentions by forcing the host to wait until the resource arbitration is complete. This signal
is active low and may need to be inverted if the host CPU wait state signal is active high.
Generic #2 mode. However, BS# is used to configure the S1D13705 for
Generic #2 mode and should be tied high (connected to IO V
high.
EPSON
DD
). RD/WR# should also be tied
S1D13705F00A APPLICATION NOTES
(X27A-G-012-01)