PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 75

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

6.2
The TBLRD instruction is used to retrieve data from
external program memory and place it into data
memory.
TBLPTR points to a byte address in external program
memory space. Executing TBLRD places the byte into
TABLAT. In addition, TBLPTR can be modified auto-
matically for the next Table Read operation.
EXAMPLE 6-1:
FIGURE 6-3:
; Read a byte from location 0020h
CLRF
CLRF
MOVLW
MOVWF
TBLRD*
2001 Microchip Technology Inc.
AD<7:0>
A<15:8>
Instruction
Execution
Memory
WRH
Cycle
WRL
BA0
ALE
Table Read
OE
TBLPTRU
TBLPTRH
20h
TBLPTRL
’1’
’1’
Q1
AAh
Opcode Fetch
TABLE READ CODE EXAMPLE
TBLRD EXTERNAL INTERFACE TIMING (8-BIT MULTIPLEXED MODE)
from 007554h
INST(PC-2)
Q2
TBLRD*
03Ah
Q3
08h
; clear upper 5 bits of TBLPTR
; clear higher 8 bits of TBLPTR
; Load 20h into
; TBLPTRL
; Data is in TABLAT
Q4
00h
Q1
Advance Information
ABh
TBLRD Cycle1
Opcode Fetch
from 007556h
MOVLW 55h
Q2
03Ah
Q3
55h
Q4
0Eh
Table Reads from external program memory are
performed one byte at a time. If the external interface is
8-bit, the bus interface circuitry in TABLAT will load the
external value into TABLAT. If the external interface is
16-bit, interface circuitry in TABLAT will select either the
high or low byte of the data from the 16-bit bus, based
on the least significant bit of the address.
Example 6-1describes how to use TBLRD. Figure 6-3
and Figure 6-4 show Table Read timings for an 8-bit
external interface, and Figure 6-5 describes Table
Read timing for a 16-bit interface.
Q1
33h
from 199E67h
TBLRD Cycle2
TABLRD 92h
Q2
CCFh
Q3
PIC18C601/801
92h
Q4
Q1
ACh
Opcode Fetch
from 007558h
ADDLW 55h
Q2
MOVLW
03Ah
Q3
55h
DS39541A-page 75
Q4
0Fh
’1’
’1’