PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 49

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

4.9
The data memory is implemented as static RAM. Each
register in the data memory has a 12-bit address, allow-
ing up to 4096 bytes of data memory. Figure 4-8 shows
the data memory organization for PIC18C601/801
devices.
The data memory map is divided into banks that con-
tain 256 bytes each. The lower four bits of the Bank
Select Register (BSR<3:0>) select which bank will be
accessed. The upper 4 bits for the BSR are not imple-
mented.
The data memory contains Special Function Registers
(SFR) and General Purpose Registers (GPR). The
SFR’s are used for control and status of the controller
and peripheral functions, while GPR’s are used for data
storage and scratch pad operations in the user’s appli-
cation. The SFR’s start at the last location of Bank 15
(0FFFh) and grow downwards. GPR’s start at the first
location of Bank 0 and grow upwards. Any read of an
unimplemented location will read as ’0’s.
GPR banks 4 and 5 serve as a Program Memory called
“Boot RAM”, when PGRM bit in MEMCON is set. When
PGRM bit is set, any read from “Boot RAM” returns ‘0’s,
while any write to it is ignored.
The entire data memory may be accessed directly or
indirectly. Direct addressing may require the use of the
BSR register. Indirect addressing requires the use of a
File Select Register (FSR). Each FSR holds a 12-bit
address value that can be used to access any location
in the Data Memory map without banking.
The instruction set and architecture allow operations
across all banks. This may be accomplished by indirect
addressing, or by the use of the MOVFF instruction. The
MOVFF instruction is a two-word/two-cycle instruction
that moves a value from one register to another.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is implemented. A segment of Bank 0 and a segment of
Bank 15 comprise the Access bank. Section 4.10 pro-
vides a detailed description of the Access bank.
2001 Microchip Technology Inc.
Data Memory Organization
Advance Information
4.9.1
The register file can be accessed either directly or indi-
rectly. Indirect addressing operates through the File
Select Registers (FSR). The operation of indirect
addressing is shown in Section 4.12.
PIC18C601/801 devices have banked memory in the
GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other RESETS.
Data RAM is available for use as GPR registers by all
instructions. Bank 15 (0F80h to 0FFFh) contains
SFR’s. All other banks of data memory contain GPR
registers starting with bank 0.
4.9.2
The Special Function Registers (SFRs) are registers
used by the CPU and Peripheral Modules for control-
ling the desired operation of the device. These regis-
ters are implemented as static RAM. A list of these
registers is given in Table 4-2.
The SFR’s can be classified into two sets: those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature.
The SFRs are typically distributed among the peripher-
als whose functions they control.
The unused SFR locations are unimplemented and
read as '0's. See Table 4-2 for addresses for the SFRs.
4.9.3
PIC18C601/801 devices contain software program-
ming options for safety critical peripherals. Because
these safety critical peripherals can be programmed in
software, registers used to control these peripherals
are given limited access by the user code. This way,
errant code will not accidentally change settings in
peripherals that could cause catastrophic results.
The registers that are considered safety critical are the
Watchdog Timer register (WDTCON), the External
Memory Control register (MEMCON), the Oscillator
Control register (OSCCON) and the Chip Select regis-
ters (CSSEL2 and CSELIO).
Two bits called Combination Lock (CMLK) bits, located
in the lower two bits of the PSPCON register, must be
set in sequence by user code to gain access to
Secured Access registers.
GENERAL PURPOSE REGISTER
FILE
SPECIAL FUNCTION REGISTERS
SECURED ACCESS REGISTERS
PIC18C601/801
DS39541A-page 49