PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 29

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

3.0
PIC18C601/801 devices differentiate between various
kinds of RESET:
a)
b)
c)
d)
e)
f)
g)
Most registers are unaffected by a RESET. Their status
is unknown on POR and unchanged by all other
RESETS. The other registers are forced to a “RESET”
state on Power-on Reset, MCLR, WDT Reset, MCLR
Reset during SLEEP, and by the RESET instruction.
FIGURE 3-1:
2001 Microchip Technology Inc.
MCLR
OSC1
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during SLEEP
Watchdog Timer (WDT) Reset during normal
operation
RESET Instruction
Stack Full Reset
Stack Underflow Reset
V
DD
Instruction
RESET
RESET
2: See Table 3-1 for time-out situations.
Pointer
Stack
RC OSC
On-chip
OST/PWRT
V
DD
Detect
Module
WDT
(1)
Rise
Stack Full/Underflow Reset
SIMPLIFIED BLOCK DIAGRAM OF THE ON-CHIP RESET CIRCUIT
OST
PWRT
WDT
Time-out
Reset
10-bit Ripple Counter
10-bit Ripple Counter
External Reset
Power-on Reset
SLEEP
Advance Information
Enable PWRT
Enable OST
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD
and POR, are set or cleared differently in different
RESET situations, as indicated in Table 3-2. These bits
are used in software to determine the nature of the
RESET. See Table 3-3 for a full description of the
RESET states of all registers.
A simplified block diagram of the on-chip RESET circuit
is shown in Figure 3-1.
PIC18C601/801 has a MCLR noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
A WDT Reset does not drive MCLR pin low.
(2)
PIC18C601/801
S
R
Q
DS39541A-page 29
Chip_Reset