PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 253

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

SUBWFB
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
2001 Microchip Technology Inc.
Decode
Q1
register ’f’
Subtract WREG from f with
Borrow
[ label ] SUBWFB f [,d [,a]]
0
d
a
(f) – (WREG) – (C)
N,OV, C, DC, Z
Subtract WREG and the carry flag
(borrow) from register 'f' (2’s com-
plement method). If 'd' is 0, the
result is stored in WREG. If 'd' is 1,
the result is stored back in register
'f' (default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
1
1
Read
Q2
0101
f
[0,1]
[0,1]
255
10da
Process
Data
Q3
ffff
dest
destination
Advance Information
Write to
Q4
ffff
SUBWFB (Cont.)
Example 1:
Example 2:
Example 3:
Before Instruction
After Instruction
Before Instruction
After Instruction
Before Instruction
After Instruction
REG
WREG
C
REG
WREG
C
Z
N
REG
WREG
C
REG
WREG
C
Z
N
REG
WREG
C
REG
WREG
C
Z
N
PIC18C601/801
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
SUBWFB
19h
0Dh
1
0Ch
0Dh
1
0
0
SUBWFB
1Bh
1Ah
0
1Bh
00h
1
1
0
SUBWFB
03h
0Eh
1
0F5h
0Eh
0
0
1
REG
( 0000 0011 )
( 0000 1101 )
( 0001 1001 )
( 0000 1101 )
( 0000 1011 )
( 0000 1101 )
( 0001 1011 )
( 0001 1010 )
; result is positive
( 0001 1011 )
; result is zero
( 1111 0100 ) [2’s comp]
( 0000 1101 )
; result is negative
REG, W
REG
DS39541A-page 253