PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 113

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

9.5
PORTE is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISE bit (= 0) will
make the corresponding PORTE pin an output (i.e., put
the contents of the output latch on the selected pin).
Read-modify-write operations on the LATE register
reads and writes the latched output value for PORTE.
PORTE is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output. PORTE is multiplexed with several peripheral
functions (Table 9-9).
PORTE is multiplexed with the system bus and is avail-
able only when the system bus is disabled, by setting
EBDIS bit in register MEMCON. When operating as the
system bus, PORTE is configured as the high order
FIGURE 9-9:
2001 Microchip Technology Inc.
Peripheral Out Select
Peripheral Data Out
Data Bus
WR LATE
or
WR PORTE
WR TRISE
Peripheral Enable
RD PORTE
Peripheral Data In
Note 1: I/O pins have diode protection to V
PORTE, TRISE and LATE
Registers
PORTE BLOCK DIAGRAM IN I/O MODE
TRIS Latch
Data Latch
D
D
CK
CK
RD TRISE
RD LATE
Q
Q
Q
Q
Advance Information
DD
Override
and V
TRIS
0
1
SS
Q
.
EN
D
byte of the address/data bus (AD15:AD8), or as the
high order address byte (A15:A8), if address and data
buses are de-multiplexed.
EXAMPLE 9-5:
CLRF
CLRF
MOVLW
MOVWF
Note:
Schmitt
Trigger
V
V
N
P
SS
DD
PORTE
LATE
03h
TRISE
On Power-on Reset, PORTE defaults to
the system bus.
PIC18C601/801
I/O pin
RE0
RE1
RE2
RE3
RE4
RE5
RE6
RE7
Pin
(1)
INITIALIZING PORTE
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RE1:RE0 as inputs
; RE7:RE2 as outputs
Override
TRIS OVERRIDE
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DS39541A-page 113
External Bus
External Bus
External Bus
External Bus
External Bus
External Bus
External Bus
External Bus
Peripheral