PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 257

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

TSTFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Example:
2001 Microchip Technology Inc.
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
If CNT
If CNT
Q1
Q1
Q1
PC
PC
register ’f’
operation
operation
operation
Test f, skip if 0
[ label ] TSTFSZ f [,a]
0
a
skip if f = 0
None
If ’f’ = 0, the next instruction, fetched
during the current instruction exe-
cution, is discarded and a NOP is
executed, making this a two-cycle
instruction. If ’a’ is 0, the Access
Bank will be selected, overriding the
BSR value. If ’a’ is 1, the Bank will
be selected as per the BSR value.
1
1(2)
Note: 3 cycles if skip and followed
HERE
NZERO
ZERO
Read
0110
No
No
No
Q2
Q2
Q2
=
=
=
=
f
[0,1]
255
by a 2-word instruction
Address ( HERE )
00h,
Address (ZERO)
00h,
Address (NZERO)
TSTFSZ
:
:
011a
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
CNT
ffff
Advance Information
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff
XORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Q1
Decode
WREG
N
Z
WREG
N
Z
PIC18C601/801
Q2
=
=
=
=
=
=
literal ’k’
Exclusive OR literal with WREG
[ label ] XORLW k
0
(WREG) .XOR. k
N,Z
The contents of WREG are
XOR’ed with the 8-bit literal 'k'. The
result is placed in WREG.
1
1
XORLW 0AFh
Read
0000
0B5h
?
?
1Ah
0
0
k
255
Q3
1010
Process
Data
DS39541A-page 257
kkkk
WREG
Q4
Write to
WREG
kkkk