PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 233

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

CPFSGT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Example:
2001 Microchip Technology Inc.
Before Instruction
operation
operation
operation
Decode
No
No
No
PC
WREG
After Instruction
If REG
If REG
Q1
Q1
Q1
PC
PC
register ’f’
operation
operation
operation
Compare f with WREG,
skip if f > WREG
[ label ] CPFSGT
0
a
(f)
skip if (f) > (WREG)
(unsigned comparison)
None
Compares the contents of data
memory location ’f’ to the contents of
the WREG by performing an
unsigned subtraction.
If the contents of ’f’ are greater than
the contents of
instruction is discarded and a NOP
is executed instead, making this a
two-cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the BSR
value.
1
1(2)
Note: 3 cycles if skip and followed
HERE
NGREATER
GREATER
Read
0110
No
No
No
Q2
Q2
Q2
=
=
>
=
=
f
[0,1]
WREG),
by a 2-word instruction.
255
Address (HERE)
?
WREG;
Address (GREATER)
WREG;
Address (NGREATER)
010a
operation
operation
operation
CPFSGT REG
:
:
Process
Data
No
No
No
Q3
Q3
Q3
,
then the fetched
ffff
f [,a]
Advance Information
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff
CPFSLT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Example:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
WREG
If REG
PC
If REG
PC
No
No
No
Q1
Q1
Q1
PIC18C601/801
register ’f’
operation
operation
operation
Compare f with WREG,
skip if f < WREG
[ label ] CPFSLT
0
a
(f) – WREG),
skip if (f) < (WREG)
(unsigned comparison)
None
Compares the contents of data
memory location 'f' to the contents
of WREG by performing an
unsigned subtraction.
If the contents of 'f' are less than the
contents of WREG, then the fetched
instruction is discarded and a NOP
is executed instead, making this a
two-cycle instruction. If ’a’ is 0, the
Access Bank will be selected. If ’a’ is
1, the Bank will be selected as per
the BSR value.
1
1(2)
Note: 3 cycles if skip and followed
HERE
NLESS
LESS
Read
0110
No
No
No
Q2
Q2
Q2
=
=
<
=
=
f
[0,1]
255
by a 2-word instruction.
Address (HERE)
?
WREG;
Address (LESS)
WREG;
Address (NLESS)
CPFSLT REG
:
:
000a
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
DS39541A-page 233
ffff
f [,a]
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff