PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 129

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

10.1
Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing the T0CS bit. In
Timer mode, the Timer0 module will increment every
instruction cycle (without prescaler). If the TMR0L reg-
ister is written, the increment is inhibited for the follow-
ing two instruction cycles. The user can work around
this by writing an adjusted value to the TMR0L register.
Counter mode is selected by setting the T0CS bit. In
Counter mode, Timer0 will increment either on every
rising, or falling edge, of pin RA4/T0CKI. The incre-
menting edge is determined by the Timer0 Source
Edge Select bit (T0SE). Clearing the T0SE bit selects
the rising edge. Restrictions on the external clock input
are discussed below.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (T
incrementing of Timer0 after synchronization.
10.2
An 8-bit counter is available as a prescaler for the
Timer0 module. The prescaler is not readable or
writable.
The PSA and T0PS2:T0PS0 bits determine the
prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF
MOVWF TMR0, BSF TMR0, x.... etc.) will clear the
prescaler count.
TABLE 10-1:
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
INTCON
TMR0H Timer0 Module’s High Byte Register
T0CON
TMR0L
TRISA
Note:
2001 Microchip Technology Inc.
Name
Timer0 Operation
Prescaler
Writing to TMR0 when the prescaler is
assigned to Timer0, will clear the prescaler
count but will not change the prescaler
assignment.
Timer0 Module’s Low Byte Register
GIE/GIEH
TMR0ON
OSC
Bit 7
—
REGISTERS ASSOCIATED WITH TIMER0
). Also, there is a delay in the actual
PORTA Data Direction Register
PEIE/GIEL TMR0IE INT0IE
T08BIT
Bit 6
T0CS
Bit 5
Advance Information
TMR0,
T0SE
Bit 4
RBIE
Bit 3
PSA
10.2.1
The prescaler assignment is fully under software con-
trol (i.e., it can be changed “on-the-fly” during program
execution).
10.3
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h in 8-bit mode, or FFFFh
to 0000h in 16-bit mode. This overflow sets the TMR0IF
bit. The interrupt can be masked by clearing the
TMR0IE bit. The TMR0IF bit must be cleared in soft-
ware by the Timer0 module Interrupt Service Routine
before re-enabling this interrupt. The TMR0 interrupt
cannot awaken the processor from SLEEP, since the
timer is shut-off during SLEEP.
10.4
Timer0 can be set in 16-bit mode by clearing T0CON
T08BIT. Registers TMR0H and TMR0L are used to
access 16-bit timer value.
TMR0H is not the high byte of the timer/counter in
16-bit mode, but is actually a buffered version of the
high byte of Timer0 (refer to Figure 10-1). The high byte
of the Timer0 counter/timer is not directly readable nor
writable. TMR0H is updated with the contents of the
high byte of Timer0 during a read of TMR0L. This pro-
vides the ability to read all 16-bits of Timer0 without
having to verify that the read of the high and low byte
were valid, due to a rollover between successive reads
of the high and low byte.
A write to the high byte of Timer0 must also take place
through the TMR0H buffer register. Timer0 high byte is
updated with the contents of the buffered value of
TMR0H, when a write occurs to TMR0L. This allows all
16-bits of Timer0 to be updated at once.
TMR0IF INT0IF
T0PS2
Bit 2
Timer0 Interrupt
16-Bit Mode Timer Reads and
Writes
SWITCHING PRESCALER
ASSIGNMENT
T0PS1 T0PS0
Bit 1
PIC18C601/801
RBIF
Bit 0
POR, BOR
xxxx xxxx
0000 0000
0000 000x
1111 1111
--11 1111
Value on
DS39541A-page 129
uuuu uuuu
0000 0000
0000 000u
1111 1111
--11 1111
Value on
RESETS
all other