UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 489

• Manufacturer Part Number: UPD78F0413GA-GAM-AX
• Description: 8BIT UC, 32K FLASH, 1KB RAM, LCD
• Manufacturer: NEC

Specifications of UPD78F0413GA-GAM-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 30
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 32KB
• Oscillator Type: External, Internal

(3) Port mode register 12 (PM12)
22.4 Operation of Low-Voltage Detector
(1) Used as reset (LVIMD = 1)
(2) Used as interrupt (LVIMD = 0)
pin is more than or less than the detection level can be checked by reading the low-voltage detection flag (LVIF: bit 0
of LVIM).
The low-voltage detector can be used in the following two modes.
While the low-voltage detector is operating, whether the supply voltage or the input voltage from an external input
When using the P120/EXLVI/INTP0 pin for external low-voltage detection potential input, set PM120 to 1. At this
time, the output latch of P120 may be 0 or 1.
PM12 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PM12 to FFH.
Remark LVIMD: Bit 1 of low-voltage detection register (LVIM)
If LVISEL = 0, compares the supply voltage (V
signal when V
If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (V
V (TYP.)), generates an internal reset signal when EXLVI < V
V
If LVISEL = 0, compares the supply voltage (V
V
If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (V
V (TYP.)). When EXLVI drops lower than V
(EXLVI
Address: FF2CH
Symbol
EXLVI
LVI
PM12
(V
.
DD
LVISEL: Bit 2 of LVIM
< V
V
EXLVI
PM120
LVI
DD
7
1
) or when V
0
1
), generates an interrupt signal (INTLVI).
< V
After reset: FFH
LVI
, and releases internal reset when V
Output mode (output buffer on)
Input mode (output buffer off)
Figure 22-4. Format of Port Mode Register 12 (PM12)
6
1
DD
becomes V
CHAPTER 22 LOW-VOLTAGE DETECTOR
R/W
5
1
User’s Manual U18698EJ1V0UD
LVI
or higher (V
EXLVI
DD
DD
P120 pin I/O mode selection
4
1
) and detection voltage (V
(EXLVI < V
) and detection voltage (V
DD
DD
V
3
1
LVI
EXLVI
EXLVI
V
), generates an interrupt signal (INTLVI).
LVI
, and releases internal reset when EXLVI
) or when EXLVI becomes V
.
2
1
LVI
LVI
). When V
), generates an internal reset
1
1
DD
PM120
drops lower than
0
EXLVI
EXLVI
EXLVI
or higher
= 1.21
= 1.21
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