UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 477

• Manufacturer Part Number: UPD78F0413GA-GAM-AX
• Description: 8BIT UC, 32K FLASH, 1KB RAM, LCD
• Manufacturer: NEC

Specifications of UPD78F0413GA-GAM-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 30
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 32KB
• Oscillator Type: External, Internal

Notes 1.
Serial interface UART6
LCD controller/driver
Manchester code
generator
Key interrupt
Reset function
Low-voltage detector
Interrupt
2.
During reset signal generation or oscillation stabilization time wait, only the PC contents among the
hardware statuses become undefined. All other hardware statuses remain unchanged after reset.
These values vary depending on the reset source.
Register
RESF
LVIM
LVIS
Table 20-2. Hardware Statuses After Reset Acknowledgment (3/3)
Reset Source
Receive buffer register 6 (RXB6)
Transmit buffer register 6 (TXB6)
Asynchronous serial interface operation mode register 6 (ASIM6)
Asynchronous serial interface reception error status register 6 (ASIS6)
Asynchronous serial interface transmission status register 6 (ASIF6)
Clock selection register 6 (CKSR6)
Baud rate generator control register 6 (BRGC6)
Asynchronous serial interface control register 6 (ASICL6)
Input switch control register (ISC)
LCD mode register (LCDMD)
LCD display mode register (LCDM)
LCD clock control register 0 (LCDC0)
Transmit buffer register (MC0TX)
Transmit bit count specification register (MC0BIT)
Control register 0 (MC0CTL0)
Control register 1 (MC0CTL1)
Control register 2 (MC0CTL2)
Status register (MC0STR)
Key return mode register (KRM)
Reset control flag register (RESF)
Low-voltage detection register (LVIM)
Low-voltage detection level selection register (LVIS)
Request flag registers 0L, 0H, 1L, 1H (IF0L, IF0H, IF1L, IF1H)
Mask flag registers 0L, 0H, 1L, 1H (MK0L, MK0H, MK1L, MK1H)
Priority specification flag registers 0L, 0H, 1L, 1H (PR0L, PR0H, PR1L,
PR1H)
External interrupt rising edge enable register (EGP)
External interrupt falling edge enable register (EGN)
WDTRF bit
LVIRF bit
Cleared (0)
Cleared (00H)
RESET Input
CHAPTER 20 RESET FUNCTION
Hardware
User’s Manual U18698EJ1V0UD
Cleared (0)
Cleared (00H)
Reset by POC
Set (1)
Held
Cleared (00H)
Reset by WDT
Held
Set (1)
Held
Reset by LVI
FFH
FFH
01H
00H
00H
00H
FFH
16H
00H
00H
00H
00H
FFH
07H
10H
00H
1FH
00H
00H
00H
00H
00H
00H
FFH
FFH
00H
00H
Acknowledgment
Status After Reset
Note 2
Note 2
Note 2
Note 1
477