UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 329

• Manufacturer Part Number: UPD78F0413GA-GAM-AX
• Description: 8BIT UC, 32K FLASH, 1KB RAM, LCD
• Manufacturer: NEC

Specifications of UPD78F0413GA-GAM-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 30
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 32KB
• Oscillator Type: External, Internal

R
(e) Reception error
(f) Noise filter of receive data
X
D0
Base clock
Parity error
Framing error
Overrun error
Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error
flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data
reception, a reception error interrupt (INTSR0) is generated.
Which error has occurred during reception can be identified by reading the contents of ASIS0 in the reception
error interrupt (INTSR0) servicing (see Figure 13-3).
The contents of ASIS0 are cleared to 0 when ASIS0 is read.
The R
If two sampled values are the same, the output of the match detector changes, and the data is sampled as
input data.
Because the circuit is configured as shown in Figure 13-11, the internal processing of the reception operation
is delayed by two clocks from the external signal status.
Reception Error
X
D0 signal is sampled using the base clock output by the prescaler block.
In
Reception of the next data is completed before data is read from receive buffer
register 0 (RXB0).
The parity specified for transmission does not match the parity of the receive data.
Stop bit is not detected.
CHAPTER 13 SERIAL INTERFACE UART0
Table 13-3. Cause of Reception Error
Q
Figure 13-11. Noise Filter Circuit
User’s Manual U18698EJ1V0UD
Internal signal A
Match detector
Cause
In
LD_EN
Q
Internal signal B
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