UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 254
![8BIT UC, 32K FLASH, 1KB RAM, LCD](/photos/19/0/190032/ge48lqfp05-40_sml.jpg)
UPD78F0413GA-GAM-AX
Manufacturer Part Number
UPD78F0413GA-GAM-AX
Description
8BIT UC, 32K FLASH, 1KB RAM, LCD
Manufacturer
NEC
Datasheet
1.UPD78F0413GA-GAM-AX.pdf
(562 pages)
Specifications of UPD78F0413GA-GAM-AX
Controller Family/series
UPD78F
No. Of I/o's
30
Ram Memory Size
1024Byte
Cpu Speed
10MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
32KB
Oscillator Type
External, Internal
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Part Number:
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(TOLEVn = 0)
<1> The count operation is enabled by setting TMHEn = 1. Start 8-bit timer counter Hn by masking one count
<2> The CMP1n register value can be changed during timer counter operation. This operation is asynchronous
<3> When the values of 8-bit timer counter Hn and the CMP0n register match, the value of 8-bit timer counter Hn
<4> If the CMP1n register value is changed, the value is latched and not transferred to the register. When the
<5> When the values of 8-bit timer counter Hn and the CMP1n register after the change match, an inactive level
<6> Clearing the TMHEn bit to 0 during timer Hn operation sets the INTTMHn signal to the default and PWM
Count clock
counter Hn
8-bit timer
INTTMHn
CMP0n
CMP1n
TMHEn
TOHn
clock to count up. At this time, PWM output outputs an inactive level.
to the count clock.
is cleared, an active level is output, and the INTTMHn signal is output.
values of the 8-bit timer counter Hn and the CMP1n register before the change match, the value is
transferred to the CMP1n register and the CMP1n register value is changed (<2>’).
However, three count clocks or more are required from when the CMP1n register value is changed to when
the value is transferred to the register. If a match signal is generated within three count clocks, the changed
value cannot be transferred to the register.
is output. 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated.
output to an inactive level.
Remark n = 0 to 2, however, TOH0 and TOH1 only for TOHn
00H 01H 02H
<1>
(e) Operation by changing CMP1n (CMP1n = 02H
02H
Figure 8-14. Operation Timing in PWM Output Mode (4/4)
80H
<2>
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2
A5H 00H 01H 02H 03H
02H (03H)
<3>
User’s Manual U18698EJ1V0UD
<2>’
<4>
A5H
03H
A5H 00H 01H 02H 03H
03H, CMP0n = A5H)
<5>
A5H 00H
<6>
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