UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 208

• Manufacturer Part Number: UPD78F0413GA-GAM-AX
• Description: 8BIT UC, 32K FLASH, 1KB RAM, LCD
• Manufacturer: NEC

Specifications of UPD78F0413GA-GAM-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 30
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 32KB
• Oscillator Type: External, Internal

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<1> Each mode of TM00 and TM52 is set.
<2> TM00, TM52, and TMH2 count operation is started. Timer operation must be started in accordance with the
Setting
(a) Set TM00 as an interval timer. Select TM52 output as the count clock.
(b) Set TM52 as an external event counter.
(c) Set TMH2 to the input enable width adjust mode (PWM mode) for the TI52 pin.
following procedure.
(a) Start TM00 counter operation by setting the TMC003 and TMC002 bits to 1 and 1.
(b) Start TM52 counter operation by setting TCE52 to 1.
(c) Start TMH2 counter operation by setting TMHE2 to 1.
Note This setting is not required if input enable for the TI52 pin is not controlled.
- TMC00:
- CRC00:
- TOC00:
- PRM00:
- CR000:
- CR010:
- TCL52:
- CR52:
- TMC52:
- TMIF52:
Caution When operating 16-bit timer/event counter 00 as an external 24-bit event counter, INTTM52
- TMHMD2: Count operation is stopped, the count clock is selected, the mode is set to input enable width
- CMP02:
- CMP12:
- ISC2:
Note This setting is not required if input enable for the TI52 pin is not controlled.
must be masked (TMMK52 = 1). Also, the compare register 52 (CR52) value must be set to
FFH.
Set to operation prohibited.
(TMC00 = 00000000B)
Set to operation as a compare register.
(CRC00 = 000000x0B, x = don’t care)
Setting TO00 pin output is prohibited upon a match between CR000 and TM00
(TOC00 = 00000000B)
TM52 output selected as a count clock.
(PRM00 = 00000111B)
Set the compare value to FFFFH.
If the compare value is set to M, TM00 will only count up to M.
Normally, CR010 is not used, however, a compare match interrupt (INTTM010) is generated
upon a match between the CR010 setting value and TM00 value.
interrupt request by using the interrupt mask flag (TMMK010).
Edge selection of TI52 pin input
Falling edge of TI52 pin →
Rising edge of TI52 pin →
Set the compare register value to FFH.
Count operation is stopped.
(TMC52 = 00000000B)
Clear this register.
adjust mode (PWM mode), the timer output level default value is set to high level, and timer
output is set to enable (TMHMD2 = 0xxx1011B, x = set based on usage conditions).
Compare value (N) frequency setting
Compare value (M) duty setting
Remark 00H
Set to ISC2 = 1 (TI52 pin input enable controlled)
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
CMP12 (M) < CMP02 (N)
User’s Manual U18698EJ1V0UD
TCL52 = 00H
TCL52 = 01H
Note
FFH
Note
Therefore, mask the