AFS600-FGG256 Actel, AFS600-FGG256 Datasheet - Page 46

FPGA - Field Programmable Gate Array 600K System Gates

AFS600-FGG256

Manufacturer Part Number
AFS600-FGG256
Description
FPGA - Field Programmable Gate Array 600K System Gates
Manufacturer
Actel
Datasheet

Specifications of AFS600-FGG256

Processor Series
AFS600
Core
IP Core
Maximum Operating Frequency
1098.9 MHz
Number Of Programmable I/os
119
Data Ram Size
110592
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
600 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AFS600-FGG256
Manufacturer:
Actel
Quantity:
135
Part Number:
AFS600-FGG256
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
AFS600-FGG256
Manufacturer:
ACTEL/爱特
Quantity:
20 000
Part Number:
AFS600-FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
AFS600-FGG256K
Manufacturer:
Microsemi SoC
Quantity:
10 000
Device Architecture
Table 2-12 • Fusion CCC/PLL Specification
2- 30
Parameter
Clock Conditioning Circuitry Input Frequency f
Clock Conditioning Circuitry Output Frequency f
Delay Increments in Programmable Delay Blocks
Number of Programmable Values in Each Programmable
Delay Block
Input Period Jitter
CCC Output Peak-to-Peak Period Jitter F
Acquisition Time
Tracking Jitter
Output Duty Cycle
Delay Range in Block: Programmable Delay 1
Delay Range in Block: Programmable Delay 2
Delay Range in Block: Fixed Delay
Notes:
1. This delay is a function of voltage and temperature. See
2. T
3. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge.
0.75 MHz to 24 MHz
24 MHz to 100 MHz
100 MHz to 250 MHz
250 MHz to 350 MHz
Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter.
J
= 25°C, VCC = 1.5 V
CCC and PLL Characteristics
Timing Characteristics
3
1, 2
CCC_OUT
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
IN_CCC
1, 2
1, 2
OUT_CCC
1, 2
Table 3-7 on page 3-9
R e visio n 1
1 Global
Network
1.00%
1.50%
2.25%
3.50%
0.025
Used
Min.
0.75
48.5
Max Peak-to-Peak Period Jitter
1.5
0.6
for deratings.
Typ.
160
2.2
Networks
3 Global
1.00%
1.50%
2.25%
3.50%
Max.
Used
51.5
5.56
5.56
350
350
300
1.5
6.0
1.6
0.8
32
MHz
MHz
Unit
ms
ps
ns
µs
ns
ns
ns
ns
ns
%

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