AFS600-FGG256 Actel, AFS600-FGG256 Datasheet - Page 205

• Manufacturer Part Number: AFS600-FGG256
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-FGG256

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 119
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-115 • Minimum and Maximum DC Input and Output Levels
Figure 2-119 • AC Loading
Table 2-116 • AC Waveforms, Measuring Points, and Capacitive Loads
1.8 V
LVCMOS
Drive
Strength
Applicable to Pro I/O Banks
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Applicable to Advanced I/O Banks
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Applicable to Standard I/O Banks
2 mA
4 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Input Low (V)
0
Note:
larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
*Measuring point = V
1.8 V LVCMOS
Low-Voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.8 V applications. It uses a 1.8 V input buffer and push-pull output buffer.
Min.
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
V
Data Path
Test Point
VIL
0.35 * VCCI 0.65 * VCCI
0.35 * VCCI 0.65 * VCCI
0.35 * VCCI 0.65 * VCCI
0.35 * VCCI 0.65 * VCCI
0.35 * VCCI 0.65 * VCCI
0.35 * VCCI 0.65 * VCCI
0.35 * VCCI 0.65 * VCCI
0.35 * VCCI 0.65 * VCCI
0.35 * VCCI 0.65 * VCCI
0.35 * VCCI 0.65 * VCCI
0.35 * VCCI 0.65 * VCCI
0.35 * VCCI 0.65 * VCCI
0.35 * VCCI 0.65 * VCCI
0.35 * VCCI 0.65 * VCCI
Max.
V
Input Low (V)
trip
. See
1.8
35 pF
Table 2-87 on page 2-168
Min.
V
VIH
Enable Path
Test Point
Max.
3.6
3.6
3.6
3.6
3.6
3.6
1.9
1.9
1.9
1.9
1.9
1.9
3.6
3.6
Measuring Point* (V)
V
R = 1 k
R e v i s i o n 1
Max.
VOL
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45 12
0.45 VCCI – 0.45 16
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45 12
0.45 VCCI – 0.45 16
0.45 VCCI – 0.45
0.45 VCCI – 0.45
V
0.9
for a complete table of trip points.
R to VCCI for t
R to GND for t
35 pF for t
5 pF for t
VOH
Min.
V
HZ
VREF (typ.) (V)
Actel Fusion Family of Mixed Signal FPGAs
mA mA
I
ZH
OL
2
4
6
8
2
4
6
8
2
4
/ t
/ t
LZ
HZ
LZ
ZHS
I
12
16
12
16
OH
2
4
6
8
2
4
6
8
2
4
–
/ t
/ t
ZL
ZH
/ t
ZL
Max.
/ t
mA
/ t
I
OSL
22
44
51
74
74
22
44
51
74
74
22
11
11
11
ZLS
/ t
ZHS
3
ZLS
Max.
I
mA
OSH
17
35
45
91
91
17
35
45
91
91
17
9
9
9
C
3
LOAD
35
µA
I
10
10
10
10
10
10
10
10
10
10
10
10
10
10
IL
(pF)
1
4
µA
2- 189
I
10
10
10
10
10
10
10
10
10
10
10
10
10
10
IH
2
4