AFS600-FGG256 Actel, AFS600-FGG256 Datasheet - Page 44

• Manufacturer Part Number: AFS600-FGG256
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-FGG256

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 119
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Architecture
2- 28
CCC Physical Implementation
The CCC circuit is composed of the following
CCC Programming
The CCC block is fully configurable. It is configured via static flash configuration bits in the array, set by
the user in the programming bitstream, or configured through an asynchronous dedicated shift register,
dynamically accessible from inside the Fusion device. The dedicated shift register permits changes of
parameters such as PLL divide ratios and delays during device operation. This latter mode allows the
user to dynamically reconfigure the PLL without the need for core programming. The register file is
accessed through a simple serial interface.
Note:
Figure 2-23 • PLL Block
CLKA
•
•
•
•
•
PLL core
3 phase selectors
6 programmable delays and 1 fixed delay
5 programmable frequency dividers that provide frequency multiplication/division (not shown in
Figure 2-23
1 dynamic shift register that provides CCC dynamic reconfiguration capability (not shown)
Clock divider and multiplier blocks are not shown in this figure or in SmartGen. They are
automatically configured based on the user's required frequencies.
Fixed Delay
PLL Core
because they are automatically configured based on the user's required frequencies)
Four-Phase Output
Programmable
Delay Type 1
R e visio n 1
(Figure
2-23):
Phase
Select
Phase
Select
Phase
Select
Programmable
Programmable
Programmable
Programmable
Programmable
Delay Type 2
Delay Type 2
Delay Type 1
Delay Type 2
Delay Type 1
GLB
GLA
GLC
YB
YC