AFS600-FGG256 Actel, AFS600-FGG256 Datasheet - Page 128
![FPGA - Field Programmable Gate Array 600K System Gates](/photos/16/15/161503/landingpageactelfusion-2_sml.jpg)
AFS600-FGG256
Manufacturer Part Number
AFS600-FGG256
Description
FPGA - Field Programmable Gate Array 600K System Gates
Manufacturer
Actel
Datasheet
1.AFS600-PQG208.pdf
(330 pages)
Specifications of AFS600-FGG256
Processor Series
AFS600
Core
IP Core
Maximum Operating Frequency
1098.9 MHz
Number Of Programmable I/os
119
Data Ram Size
110592
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
600 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AFS600-FGG256
Manufacturer:
Actel
Quantity:
135
Part Number:
AFS600-FGG256
Manufacturer:
ACTEL/爱特
Quantity:
20 000
Company:
Part Number:
AFS600-FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
AFS600-FGG256K
Manufacturer:
Microsemi SoC
Quantity:
10 000
- Current page: 128 of 330
- Download datasheet (13Mb)
Device Architecture
2- 11 2
Terminology
Conversion time is the interval between the release of the hold state (imposed by the input circuitry of a
track-and-hold) and the instant at which the voltage on the sampling capacitor settles to within one LSB
of a new input value.
For an ideal ADC, the analog-input levels that trigger any two successive output codes should differ by
one LSB (DNL = 0). Any deviation from one LSB in defined as DNL
Figure 2-87 • Differential Non-Linearity (DNL)
ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An
ideal ADC’s error consists only of quantization of noise. As the input frequency increases, the overall
noise (particularly in the distortion components) also increases, thereby reducing the ENOB and SINAD
(also see “Signal-to-Noise and Distortion Ratio (SINAD)”.) ENOB for a full-scale, sinusoidal input
waveform is computed using
Full-scale error is the difference between the actual value that triggers that transition to full-scale and the
ideal analog full-scale transition value. Full-scale error equals offset error plus gain error.
Conversion Time
DNL – Differential Non-Linearity
ENOB – Effective Number of Bits
FS Error – Full-Scale Error
Error = –0.5 LSB
EQ
21.
Input Voltage to Prescaler
ENOB
R e visio n 1
Ideal Output
=
SINAD 1.76
------------------------------------ -
6.02
Error = +1 LSB
–
Actual Output
(Figure
2-87).
EQ 21
Related parts for AFS600-FGG256
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![AFS600-1FGG256I](/images/manufacturer_photos/0/0/8/actel_tmb.jpg)
Part Number:
Description:
AFS600-1FGG256I
Manufacturer:
Actel
Datasheet:
![AFS600-2FGG256I](/images/manufacturer_photos/0/0/8/actel_tmb.jpg)
Part Number:
Description:
AFS600-2FGG256I
Manufacturer:
Actel
Datasheet: