AFS600-FGG256 Actel, AFS600-FGG256 Datasheet - Page 161

• Manufacturer Part Number: AFS600-FGG256
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-FGG256

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 119
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-72 • Fusion Standard and Advanced I/O – Hot-Swap and 5 V Input Tolerance Capabilities
Table 2-73 • Fusion Pro I/O – Hot-Swap and 5 V Input Tolerance Capabilities
I/O Assignment
3.3 V LVTTL/LVCMOS
3.3 V PCI, 3.3 V PCI-X
LVCMOS 2.5 V
LVCMOS 2.5 V / 5.0 V
LVCMOS 1.8 V
LVCMOS 1.5 V
Differential,
LVDS/BLVDS/M-
LVDS/ LVPECL
Notes:
1. Can be implemented with an external IDT bus switch, resistor divider, or Zener with resistor.
2. Can be implemented with an external resistor and an internal clamp diode.
3. Bidirectional LVPECL buffers are not supported. I/Os can be configured as either input buffers or output buffers.
I/O Assignment
3.3 V LVTTL/LVCMOS
3.3 V PCI, 3.3 V PCI-X
LVCMOS 2.5 V
LVCMOS 2.5 V / 5.0 V
LVCMOS 1.8 V
LVCMOS 1.5 V
Voltage-Referenced Input Buffer
Differential, LVDS/BLVDS/M-LVDS/LVPECL
Notes:
1. Can be implemented with an external IDT bus switch, resistor divider, or Zener with resistor.
2. Can be implemented with an external resistor and an internal clamp diode.
3. In the
4. Bidirectional LVPECL buffers are not supported. I/Os can be configured as either input buffers or output buffers.
LVCMOS5 macro for the LVCMOS 2.5 V / 5.0 V I/O standard or the LVCMOS25 macro for the LVCMOS 2.5 V I/O
standard.
SmartGen, FlashROM, Flash Memory System Builder, and Analog System Builder User's
Electrostatic Discharge (ESD) Protection
Fusion devices are tested per JEDEC Standard JESD22-A114-B.
Fusion devices contain clamp diodes at every I/O, global, and power pad. Clamp diodes protect all
device pads against damage from ESD as well as from excessive voltage transients.
Each I/O has two clamp diodes. One diode has its positive (P) side connected to the pad and its negative
(N) side connected to V
to the pad. During operation, these diodes are normally biased in the Off state, except when transient
voltage is significantly above V
By selecting the appropriate I/O configuration, the diode is turned on or off. Refer to
Table 2-73 on page 2-145
The second diode is always connected to the pad, regardless of the I/O configuration selected.
3
3
3
Standard
N/A
N/A
N/A
I/O
No
No
No
No
Clamp Diode
Advanced
CCI
Yes
Yes
Yes
Yes
Yes
Yes
Yes
I/O
for more information about I/O standards and the clamp diode.
. The second diode has its P side connected to GND and its N side connected
CCI
4
or below GND levels.
Standard
Clamp
Diode
Yes
Yes
N/A
Yes
N/A
Yes
Yes
N/A
No
No
No
No
No
No
Yes
I/O
Hot Insertion
R e v i s i o n 1
Insertion
Advanced
Hot
Yes
Yes
Yes
Yes
Yes
Yes
No
No
I/O
No
No
No
No
No
No
No
Tolerance
5 V Input Tolerance
5 V Input
Standard
Yes
Yes
Yes
Yes
N/A
N/A
N/A
No
No
No
No
No
I/O
No
No
No
Actel Fusion Family of Mixed Signal FPGAs
1
1
2
1
Advanced
Input Buffer
Yes
Yes
Yes
I/O
No
No
No
No
1
1
2
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
1
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Buffer
Input
Guide, select the
Output Buffer
Table 2-72
Output
Buffer
2- 145
and