AFS600-FGG256 Actel, AFS600-FGG256 Datasheet - Page 11

• Manufacturer Part Number: AFS600-FGG256
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-FGG256

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 119
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 1-1 • Analog Quad
Off-Chip
On-Chip
Pads
Power
of the power supply. The AC pad measures the voltage drop across an external sense resistor to
calculate current. The AG MOSFET gate driver pad turns the external MOSFET on and off. The AT pad
measures the load-side voltage level.
Embedded Memories
Flash Memory Blocks
The flash memory available in each Fusion device is composed of one to four flash blocks, each 2 Mbits
in density. Each block operates independently with a dedicated flash controller and interface. Fusion
flash memory blocks combine fast access times (60 ns random access and 10 ns access in Read-Ahead
mode) with a configurable 8-, 16-, or 32-bit datapath, enabling high-speed flash operation without wait
states. The memory block is organized in pages and sectors. Each page has 128 bytes, with 33 pages
comprising one sector and 64 sectors per block. The flash block can support multiple partitions. The only
constraint on size is that partition boundaries must coincide with page boundaries. The flexibility and
granularity enable many use models and allow added granularity in programming updates.
Fusion devices support two methods of external access to the flash memory blocks. The first method is a
serial interface that features a built-in JTAG-compliant port, which allows in-system programmability
during user or monitor/test modes. This serial interface supports programming of an AES-encrypted
stream. Secure data can be passed through the JTAG interface, decrypted, and then programmed in the
flash block. The second method is a soft parallel interface.
FPGA logic or an on-chip soft microprocessor can access flash memory through the parallel interface.
Since the flash parallel interface is implemented in the FPGA fabric, it can potentially be customized to
meet special user requirements. For more information, refer to the
memory parallel interface provides configurable byte-wide (×8), word-wide (×16), or dual-word-wide
AV
Digital
Input
scaler
Pre-
Monitor Block
Voltage
(DAVOUTx)
Line Side
To FPGA
To Analog MUX
Monitor/Instr
AC
Amplifier
Digital
Current
Input
scaler
Pre-
Monitor Block
(DACOUTx)
Current
To FPGA
Analog Quad
To Analog MUX
R e v i s i o n 1
R
pullup
From FPGA
Gate Driver
MOSFET
(GDONx)
Power
AG
Actel Fusion Family of Mixed Signal FPGAs
Driver
Gate
CoreCFI Handbook.
AT
Temperature
Digital
Input
Monitor
scaler
Pre-
Monitor Block
Load Side
Temperature
(DATOUTx)
To FPGA
To Analog MUX
The flash
1 -5