AFS600-FGG256 Actel, AFS600-FGG256 Datasheet - Page 258

FPGA - Field Programmable Gate Array 600K System Gates

AFS600-FGG256

Manufacturer Part Number
AFS600-FGG256
Description
FPGA - Field Programmable Gate Array 600K System Gates
Manufacturer
Actel
Datasheet

Specifications of AFS600-FGG256

Processor Series
AFS600
Core
IP Core
Maximum Operating Frequency
1098.9 MHz
Number Of Programmable I/os
119
Data Ram Size
110592
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
600 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
AFS600-FGG256
Manufacturer:
Actel
Quantity:
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Quantity:
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Part Number:
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DC and Power Characteristics
3 - 8
Theta-JA
Junction-to-ambient thermal resistance (θ
JEDEC (JESD-51), but it has little relevance in actual performance of the product. It should be used with
caution but is useful for comparing the thermal performance of one package to another.
A sample calculation showing the maximum power dissipation allowed for the AFS600-FG484 package
under forced convection of 1.0 m/s and 75°C ambient temperature is as follows:
where
The power consumption of a device can be calculated using the Actel power calculator. The device's
power consumption must be lower than the calculated maximum power dissipation by the package. If the
power consumption is higher than the device's maximum allowable power dissipation, a heat sink can be
attached on top of the case, or the airflow inside the system must be increased.
Theta-JB
Junction-to-board thermal resistance (θ
surface of the chip to the PCB. As defined by the JEDEC (JESD-51) standard, the thermal resistance
from junction to board uses an isothermal ring cold plate zone concept. The ring cold plate is simply a
means to generate an isothermal boundary condition at the perimeter. The cold plate is mounted on a
JEDEC standard board with a minimum distance of 5.0 mm away from the package edge.
Theta-JC
Junction-to-case thermal resistance (θ
surface of the chip to the top or bottom surface of the package. It is applicable for packages used with
external heat sinks. Constant temperature is applied to the surface in consideration and acts as a
boundary condition. This only applies to situations where all or nearly all of the heat is dissipated through
the surface in consideration.
Calculation for Heat Sink
For example, in a design implemented in an AFS600-FG484 package with 2.5 m/s airflow, the power
consumption value using the power calculator is 3.00 W. The user-dependent T
follows:
From the datasheet:
θ
T
T
T
θ
θ
JA
A
A
JA
JC
J
=
=
= 19.00°C/W (taken from
= 75.00°C
=
=
100.00°C
70.00°C
17.00°C/W
8.28°C/W
Maximum Power Allowed
Maximum Power Allowed
P
Table 3-6 on page
=
T
------------------ -
J
θ
JB
JC
JA
) measures the ability of the package to dissipate heat from the
) measures the ability of a device to dissipate heat from the
T
A
JA
R e vi s i o n 1
=
) is determined under standard conditions specified by
100°C 70°C
----------------------------------- -
=
17.00 W
100.00°C 75.00°C
----------------------------------------------------
3-7).
=
19.00°C/W
T
-------------------------------------------- -
J(MAX)
=
θ
1.76 W
JA
T
A(MAX)
=
1.3 W
a
and T
j
are given as
EQ 4
EQ 5
EQ 6

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