AFS600-FGG256 Actel, AFS600-FGG256 Datasheet - Page 21

FPGA - Field Programmable Gate Array 600K System Gates

AFS600-FGG256

Manufacturer Part Number
AFS600-FGG256
Description
FPGA - Field Programmable Gate Array 600K System Gates
Manufacturer
Actel
Datasheet

Specifications of AFS600-FGG256

Processor Series
AFS600
Core
IP Core
Maximum Operating Frequency
1098.9 MHz
Number Of Programmable I/os
119
Data Ram Size
110592
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
600 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Table 2-1 • Combinatorial Cell Propagation Delays
Combinatorial Cell
INV
AND2
NAND2
OR2
NOR2
XOR2
MAJ3
XOR3
MUX2
AND3
Note:
For the derating values at specific junction temperature and voltage supply levels, refer to
page
Commercial Temperature Range Conditions: T
Sample VersaTile Specifications—Sequential Module
The Fusion library offers a wide variety of sequential cells, including flip-flops and latches. Each has a
data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a
representative sample from the library
ProASIC3/E Macro Library
3-9.
Timing Characteristics
Y = MAJ(A, B, C)
Y = A
Y = A !S + B S
Y = A · B · C
Y = !(A + B)
Y = !(A · B)
Y = A
Equation
Y = A + B
Y = A · B
Y = !A
B
B
Guide.
C
Parameter
t
t
t
t
t
t
t
t
t
t
(Figure
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
R e v i s i o n 1
2-5). For more details, refer to the
J
= 70°C, Worst-Case VCC = 1.425 V
0.40
0.47
0.47
0.49
0.49
0.74
0.70
0.87
0.51
0.56
–2
Actel Fusion Family of Mixed Signal FPGAs
0.46
0.54
0.54
0.55
0.55
0.84
0.79
1.00
0.58
0.64
–1
0.54
0.63
0.63
0.65
0.65
0.99
0.93
1.17
0.68
0.75
Std.
Fusion, IGLOO/e and
Table 3-7 on
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2 -5

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