ATA5771-DK1 Atmel, ATA5771-DK1 Datasheet - Page 86

• Manufacturer Part Number: ATA5771-DK1
• Description: BOARD XMITTER FOR ATA5771 868MHZ
• Manufacturer: Atmel
• Type: Transmitterr

Specifications of ATA5771-DK1

• Frequency: 868MHz
• Maximum Frequency: 868 MHz
• Supply Voltage (max): 4 V
• Supply Voltage (min): 2 V
• Supply Current: 8.5 mA
• Product: RF Development Tools
• For Use With/related Products: ATA5771
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.15.8
86
Atmel ATA5771/73/74
Timer/Counter Timing Diagrams
The PWM waveform is generated by clearing (or setting) the OC0x Register at the Compare
Match between OCR0x and TCNT0 when the counter increments, and setting (or clearing) the
OC0x Register at Compare Match between OCR0x and TCNT0 when the counter decre-
ments. The PWM frequency for the output when using phase correct PWM can be calculated
by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in
even though there is no Compare Match. The point of this transition is to guaratee symmetry
around BOTTOM. There are two cases that give a transition without Compare Match.
• OCR0A changes its value from MAX, like in
• The timer starts counting from a value higher than the one in OCR0A, and for that reason
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set.
shows the count sequence close to the MAX value in all modes other than phase correct PWM
mode.
Figure 4-33. Timer/Counter Timing Diagram, no Prescaling
is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To
ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of
an up-counting Compare Match.
misses the Compare Match and hence the OCn change that would have happened on the
way up.
TCNTn
(clk
TOVn
clk
clk
I/O
I/O
Tn
/1)
Figure 4-33
MAX - 1
contains timing data for basic Timer/Counter operation. The figure
Figure 4-32 on page 85
f
OCnxPCPWM
MAX
Figure 4-32 on page
=
-------------------- -
N
f
clk_I/O
510
OCn has a transition from high to low
BOTTOM
85. When the OCR0A value
T0
) is therefore shown as a
BOTTOM + 1
9137E–RKE–12/10