ATA5771-DK1 Atmel, ATA5771-DK1 Datasheet - Page 38

• Manufacturer Part Number: ATA5771-DK1
• Description: BOARD XMITTER FOR ATA5771 868MHZ
• Manufacturer: Atmel
• Type: Transmitterr

Specifications of ATA5771-DK1

• Frequency: 868MHz
• Maximum Frequency: 868 MHz
• Supply Voltage (max): 4 V
• Supply Voltage (min): 2 V
• Supply Current: 8.5 mA
• Product: RF Development Tools
• For Use With/related Products: ATA5771
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.9.8
4.9.9
4.9.9.1
38
Atmel ATA5771/73/74
128 kHz Internal Oscillator
System Clock Prescaler
Switching Time
The 128kHz internal Oscillator is a low power Oscillator providing a clock of 128kHz. The fre-
quency is nominal at 3V and 25°C. This clock may be select as the system clock by
programming the CKSEL Fuses to “0100”.
When this clock source is selected, start-up times are determined by the SUT Fuses as shown
in
Table 4-11.
The Atmel
CLKPR. This feature can be used to decrease power consumption when the requirement for
processing power is low. This can be used with all clock source options, and it will affect the
clock frequency of the CPU and all synchronous peripherals. clk
are divided by a factor as shown in
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occur in the clock system and that no intermediate frequency is higher than neither
the clock frequency corresponding to the previous setting, nor the clock frequency corre-
sponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the
state of the prescaler – even if it were readable, and the exact time it takes to switch from one
clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before
the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1
is the previous clock period, and T2 is the period corresponding to the new prescaler setting.
SUT1..0
Table
00
01
10
11
4-11.
®
ATtiny44V system clock can be divided by setting the Clock Prescale Register –
Power-down and Power-save
Start-up Times for the 128 kHz Internal Oscillator
Start-up Time from
6 CK
6 CK
6 CK
Table 4-12 on page
Additional Delay from
Reserved
14CK + 64 ms
14CK + 4 ms
Reset
14CK
40.
I/O
, clk
BOD enabled
Fast rising power
Slowly rising power
ADC
Recommended Usage
, clk
CPU
9137E–RKE–12/10
, and clk
FLASH