ATA5771-DK1 Atmel, ATA5771-DK1 Datasheet - Page 84

• Manufacturer Part Number: ATA5771-DK1
• Description: BOARD XMITTER FOR ATA5771 868MHZ
• Manufacturer: Atmel
• Type: Transmitterr

Specifications of ATA5771-DK1

• Frequency: 868MHz
• Maximum Frequency: 868 MHz
• Supply Voltage (max): 4 V
• Supply Voltage (min): 2 V
• Supply Current: 8.5 mA
• Product: RF Development Tools
• For Use With/related Products: ATA5771
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

84
Atmel ATA5771/73/74
Figure 4-31. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the
interrupt is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.
Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM out-
put can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one
allowes the AC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not
available for the OC0B pin (See
visible on the port pin if the data direction for the port pin is set as output. The PWM waveform
is generated by setting (or clearing) the OC0x Register at the Compare Match between
OCR0x and TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the
counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represents special cases when generating a
PWM waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the out-
put will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX
will result in a constantly high or low output (depending on the polarity of the output set by the
COM0A1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by
setting OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1). The wave-
form generated will have a maximum frequency of
This feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the
Output Compare unit is enabled in the fast PWM mode.
TCNTn
OCn
OCn
Period
1
2
3
Table 4-32 on page
f
OCnxPWM
4
=
5
-------------------- -
N
f
clk_I/O
0
88). The actual OC0x value will only be
256
= f
6
clk_I/O
/2 when OCR0A is set to zero.
7
OCRnx Interrupt Flag Set
OCRnx Update and
TOVn Interrupt Flag Set
(COMnx1:0 = 2)
(COMnx1:0 = 3)
9137E–RKE–12/10