ATA5771-DK1 Atmel, ATA5771-DK1 Datasheet - Page 138

• Manufacturer Part Number: ATA5771-DK1
• Description: BOARD XMITTER FOR ATA5771 868MHZ
• Manufacturer: Atmel
• Type: Transmitterr

Specifications of ATA5771-DK1

• Frequency: 868MHz
• Maximum Frequency: 868 MHz
• Supply Voltage (max): 4 V
• Supply Voltage (min): 2 V
• Supply Current: 8.5 mA
• Product: RF Development Tools
• For Use With/related Products: ATA5771
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.19.2
4.19.2.1
4.19.2.2
138
Atmel ATA5771/73/74
Register Description
ADCSRB – ADC Control and Status Register B
ACSR – Analog Comparator Control and Status Register
• Bit 6 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the
ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written
logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed
description of this bit, see
• Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the Analog Comparator is switched off. This bit
can be set at any time to turn off the Analog Comparator. This will reduce power consumption
in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must
be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is
changed.
• Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Ana-
log Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog
Comparator.
• Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to ACO.
The synchronization introduces a delay of 1 - 2 clock cycles.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined
by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is
set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog
Comparator interrupt is activated. When written logic zero, the interrupt is disabled.
Bit
0x03 (0x23)
Read/Write
Initial Value
Bit
0x08 (0x28)
Read/Write
Initial Value
ACD
R/W
R/W
BIN
7
0
7
0
ACBG
ACME
R/W
R/W
Section 4.19.1 “Analog Comparator Multiplexed Input” on page
6
0
6
0
ACO
R/W
N/A
5
R
5
–
0
ADLAR
R/W
ACI
R/w
4
0
4
0
ACIE
R/W
R
3
0
3
–
0
ADTS2
ACIC
R/W
R/W
2
0
2
0
ADTS1
ACIS1
R/W
R/W
1
0
1
0
ADTS0
ACIS0
R/W
R/W
0
0
0
0
9137E–RKE–12/10
ADCSRB
ACSR
137.