ATA5771-DK1 Atmel, ATA5771-DK1 Datasheet - Page 121

• Manufacturer Part Number: ATA5771-DK1
• Description: BOARD XMITTER FOR ATA5771 868MHZ
• Manufacturer: Atmel
• Type: Transmitterr

Specifications of ATA5771-DK1

• Frequency: 868MHz
• Maximum Frequency: 868 MHz
• Supply Voltage (max): 4 V
• Supply Voltage (min): 2 V
• Supply Current: 8.5 mA
• Product: RF Development Tools
• For Use With/related Products: ATA5771
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.16.11.7
4.16.11.8
9137E–RKE–12/10
ICR1H and ICR1L – Input Capture Register 1
TIMSK1 – Timer/Counter Interrupt Mask Register 1
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on
the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input
Capture can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are
read simultaneously when the CPU accesses these registers, the access is performed using
an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other
16-bit registers.
• Bit 7,6,4,3 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must
be written to zero when the register is written.
• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Input Capture interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 66.) is executed when the
ICF1 Flag, located in TIFR1, is set.
• Bit 2– OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The correspond-
ing Interrupt Vector (see
flag, located in TIFR1, is set.
• Bit 1– OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The correspond-
ing Interrupt Vector (see
flag, located in TIFR1, is set.
• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vec-
tor (see
TIFR1, is set.
Bit
0x25 (0x45)
0x24 (0x44)
Read/Write
Initial Value
Bit
0x0C (0x2C)
Read/Write
Initial Value
Section 4.12 “Interrupts” on page
R/W
Section 4.16.3 “Accessing 16-bit Registers” on page
R
7
0
7
–
0
R/W
Section 4.12 “Interrupts” on page
Section 4.12 “Interrupts” on page
R
6
0
6
–
0
ICIE1
R/W
R/W
5
0
5
0
R/W
4
0
R
4
–
0
55) is executed when the TOV1 flag, located in
ICR1[15:8]
ICR1[7:0]
R/W
3
0
Atmel ATA5771/73/74
R
3
–
0
OCIE1B
55) is executed when the OCF1B
55) is executed when the OCF1A
R/W
R/W
2
0
2
0
OCIE1A
R/W
97.
R/W
1
0
1
0
R/W
TOIE1
R/W
0
0
0
0
TIMSK1
ICR1H
ICR1L
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