ATA5771-DK1 Atmel, ATA5771-DK1 Datasheet - Page 134
ATA5771-DK1
Manufacturer Part Number
ATA5771-DK1
Description
BOARD XMITTER FOR ATA5771 868MHZ
Manufacturer
Atmel
Type
Transmitterr
Specifications of ATA5771-DK1
Frequency
868MHz
Maximum Frequency
868 MHz
Supply Voltage (max)
4 V
Supply Voltage (min)
2 V
Supply Current
8.5 mA
Product
RF Development Tools
For Use With/related Products
ATA5771
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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4.18.5.4
134
Atmel ATA5771/73/74
USICR – USI Control Register
• Bit 6 – USIOIF: Counter Overflow Interrupt Flag
This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). An
interrupt will be generated when the flag is set while the USIOIE bit in USICR and the Global
Interrupt Enable Flag are set. The flag is cleared if a one is written to the USIOIF bit or by
reading the USIBR register. Clearing this bit will release the counter overflow hold of SCL in
Two-wire mode.
A counter overflow interrupt will wakeup the processor from Idle sleep mode.
• Bit 5 – USIPF: Stop Condition Flag
When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is
detected. The flag is cleared by writing a one to this bit. Note that this is not an Interrupt Flag.
This signal is useful when implementing Two-wire bus master arbitration.
• Bit 4 – USIDC: Data Output Collision
This bit is logical one when bit 7 in the Shift Register differs from the physical pin value. The
flag is only valid when Two-wire mode is used. This signal is useful when implementing
Two-wire bus master arbitration.
• Bits 3..0 – USICNT3..0: Counter Value
These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read
or written by the CPU.
The 4-bit counter increments by one for each clock generated either by the external clock
edge detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC
strobe bits. The clock source depends of the setting of the USICS1..0 bits. For external clock
operation a special feature is added that allows the clock to be generated by writing to the
USITC strobe bit. This feature is enabled by write a one to the USICLK bit while setting an
external clock source (USICS1 = 1).
Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input
(USCK/SCL) are can still be used by the counter.
The Control Register includes interrupt enable control, wire mode setting, Clock Select setting,
and clock strobe.
• Bit 7 – USISIE: Start Condition Interrupt Enable
Setting this bit to one enables the Start Condition detector interrupt. If there is a pending inter-
rupt when the USISIE and the Global Interrupt Enable Flag is set to one, this will immediately
be executed. See the USISIF bit description in
further details.
Bit
0x0D (0x2D)
Read/Write
Initial Value
USISIE
R/W
7
0
USIOIE
R/W
0
6
USIWM1
R/W
5
0
USIWM0
R/W
4
0
“USISR – USI Status Register” on page 133
USICS1
R/W
3
0
USICS0
R/W
2
0
USICLK
W
1
0
USITC
W
9137E–RKE–12/10
0
0
USICR
for
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