ATA5771-DK1 Atmel, ATA5771-DK1 Datasheet - Page 83

• Manufacturer Part Number: ATA5771-DK1
• Description: BOARD XMITTER FOR ATA5771 868MHZ
• Manufacturer: Atmel
• Type: Transmitterr

Specifications of ATA5771-DK1

• Frequency: 868MHz
• Maximum Frequency: 868 MHz
• Supply Voltage (max): 4 V
• Supply Voltage (min): 2 V
• Supply Current: 8.5 mA
• Product: RF Development Tools
• For Use With/related Products: ATA5771
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.15.7.3
9137E–RKE–12/10
Fast PWM Mode
For generating a waveform output in CTC mode, the OC0A output can be set to toggle its log-
ical level on each Compare Match by setting the Compare Output mode bits to toggle mode
(COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction
for the pin is set to output. The waveform generated will have a maximum frequency of
0
lowing equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that
the counter counts from MAX to 0x00.
The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high fre-
quency PWM waveform generation option. The fast PWM differs from the other PWM option
by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from
BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7. In
non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare
Match between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode,
the output is set on Compare Match and cleared at BOTTOM. Due to the single-slope opera-
tion, the operating frequency of the fast PWM mode can be twice as high as the phase correct
PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode
well suited for power regulation, rectification, and DAC applications. High frequency allows
physically small sized external components (coils, capacitors), and therefore reduces total
system cost.
In fast PWM mode, the counter is incremented until the counter value matches the TOP value.
The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
PWM mode is shown in
histogram for illustrating the single-slope operation. The diagram includes non-inverted and
inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Com-
pare Matches between OCR0x and TCNT0.
= f
clk_I/O
/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the fol-
Figure
f
4-31. The TCNT0 value is in the timing diagram shown as a
OCnx
=
------------------------------------------------------ -
2
N
f
clk_I/O
1
+
Atmel ATA5771/73/74
OCRnx
83