HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 820
![IC H8 MCU FLASH 128K 100QFP](/photos/12/21/122166/qfp100-g1_pkg_sml.jpg)
HD64F3048BF25
Manufacturer Part Number
HD64F3048BF25
Description
IC H8 MCU FLASH 128K 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.DF3048BF25V.pdf
(903 pages)
Specifications of HD64F3048BF25
Core Processor
H8/300H
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3048BF25
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD64F3048BF25V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 820 of 903
- Download datasheet (5Mb)
Appendix B Internal I/O Register
TSR3—Timer Status Register 3
TCNT3 H/L—Timer Counter 3 H/L
GRA3 H/L—General Register A3 H/L
Rev. 3.00 Sep 27, 2006 page 792 of 872
REJ09B0325-0300
Bit
Initial value
Read/Write
Note: * Only 0 can be written, to clear the flag.
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
R/W
R/W
15
15
0
1
7
1
R/W
R/W
14
14
0
1
R/W
R/W
Output compare or input capture register (can be buffered)
13
13
0
1
Overflow flag
0 [Clearing condition]
1 [Setting condition]
6
1
R/W
R/W
12
12
Read OVF when OVF = 1, then write 1 in OVF
TCNT overflowed from H'FFFF to H'0000 or underflowed from
H'0000 to H'FFFF
0
1
Complementary PWM mode:
Other modes:
R/W
R/W
11
11
0
1
5
1
R/W
R/W
10
10
0
1
R/W
R/W
9
0
9
1
4
1
R/W
R/W
8
0
8
1
R/W
R/W
7
0
7
1
3
1
R/W
R/W
6
0
6
1
up/down counter
up-counter
R/W
R/W
H'85
H'86, H'87
H'88, H'89
R/(W)
5
0
5
1
OVF
2
0
R/W
R/W
4
0
4
1
*
Bit functions are the
same as for ITU0
R/W
R/W
R/(W)
3
0
3
1
IMFB
1
0
R/W
R/W
2
0
2
1
*
R/W
R/W
R/(W)
1
0
1
1
IMFA
0
0
ITU3
ITU3
ITU3
R/W
R/W
0
0
0
1
*
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