HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 237
![IC H8 MCU FLASH 128K 100QFP](/photos/12/21/122166/qfp100-g1_pkg_sml.jpg)
HD64F3048BF25
Manufacturer Part Number
HD64F3048BF25
Description
IC H8 MCU FLASH 128K 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.DF3048BF25V.pdf
(903 pages)
Specifications of HD64F3048BF25
Core Processor
H8/300H
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3048BF25
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD64F3048BF25V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 237 of 903
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Bit 6—Data Transfer Size (DTSZ): Selects the data size of each transfer.
Bit 5—Data Transfer Increment/Decrement (DTID): Selects whether to increment or
decrement the memory address register (MAR) after a data transfer in I/O mode or repeat mode.
MAR is not incremented or decremented in idle mode.
Bit 4—Repeat Enable (RPE): Selects whether to transfer data in I/O mode, idle mode, or repeat
mode.
Operations in these modes are described in sections 8.4.2, I/O Mode, 8.4.3, Idle Mode, and 8.4.4,
Repeat Mode.
Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND)
requested when the DTE bit is cleared to 0.
Bit 6: DTSZ
0
1
Bit 5: DTID
0
1
Bit 4: RPE
0
1
Bit 3: DTIE
0
1
Description
Byte-size transfer
Word-size transfer
Description
MAR is incremented after each data transfer
MAR is decremented after each data transfer
Bit 3: DTIE
0
1
0
1
Description
The DEND interrupt requested by DTE is disabled
The DEND interrupt requested by DTE is enabled
If DTSZ = 0, MAR is incremented by 1 after each transfer
If DTSZ = 1, MAR is incremented by 2 after each transfer
If DTSZ = 0, MAR is decremented by 1 after each transfer
If DTSZ = 1, MAR is decremented by 2 after each transfer
Description
I/O mode
Repeat mode
Idle mode
Rev. 3.00 Sep 27, 2006 page 209 of 872
Section 8 DMA Controller
REJ09B0325-0300
(Initial value)
(Initial value)
(Initial value)
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