HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 147
HD64F3048BF25
Manufacturer Part Number
HD64F3048BF25
Description
IC H8 MCU FLASH 128K 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.DF3048BF25V.pdf
(903 pages)
Specifications of HD64F3048BF25
Core Processor
H8/300H
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3048BF25
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD64F3048BF25V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 147 of 903
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5.5.2
The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after
determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is
currently executing one of these interrupt-inhibiting instructions, however, when the instruction is
completed the CPU always continues by executing the next instruction.
5.5.3
The EEPMOV.B and EEPMOV.W instructions differ in their reaction to interrupt requests.
When the EEPMOV.B instruction is executing a transfer, no interrupts are accepted until the
transfer is completed, not even NMI.
When the EEPMOV.W instruction is executing a transfer, interrupt requests other than NMI are
not accepted until the transfer is completed. If NMI is requested, NMI exception handling starts at
a transfer cycle boundary. The PC value saved on the stack is the address of the next instruction.
Programs should be coded as follows to allow for NMI interrupts during EEPMOV.W execution:
5.5.4
The IRQnF flag specification calls for the flag to be cleared by writing 0 to it after it has been read
while set to 1. However, it is possible for the IRQnF flag to be cleared by mistake simply by
writing 0 to it, irrespective of whether it has been read while set to 1, with the result that interrupt
exception handling is not executed. This occurs when the following conditions are fulfilled.
L1: EEPMOV.W
Setting conditions
1. Multiple external interrupts (IRQa, IRQb) are being used.
2. Different clearing methods are being used: clearing by writing 0 for the IRQaF flag, and
3. A bit manipulation instruction is used on the IRQ status register to clear the IRQaF flag, or
clearing by hardware for the IRQbF flag.
else ISR is read as a byte unit, the IRQaF flag bit is cleared, and the values read in the other
bits are written as a byte unit.
MOV.W R4,R4
BNE
Instructions That Inhibit Interrupts
Interrupts during EEPMOV Instruction Execution
Usage Notes on External Interrupts
L1
Rev. 3.00 Sep 27, 2006 page 119 of 872
Section 5 Interrupt Controller
REJ09B0325-0300
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