HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 308
![IC H8 MCU FLASH 128K 100QFP](/photos/12/21/122166/qfp100-g1_pkg_sml.jpg)
HD64F3048BF25
Manufacturer Part Number
HD64F3048BF25
Description
IC H8 MCU FLASH 128K 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.DF3048BF25V.pdf
(903 pages)
Specifications of HD64F3048BF25
Core Processor
H8/300H
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3048BF25
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD64F3048BF25V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 308 of 903
- Download datasheet (5Mb)
Section 9 I/O Ports
9.7
9.7.1
Port 6 is a 7-bit input/output port that is also used for input and output of bus control signals
(LWR, HWR, RD, AS, BACK, BREQ, and WAIT). When DRAM is connected to area 3, LWR,
HWR, and RD also function as LW, UW, and CAS, or LCAS, UCAS, and WE, respectively. For
details see section 7, Refresh Controller.
Figure 9.6 shows the pin configuration of port 6. In modes 1 to 6 (expanded modes) the pin
functions are LWR, HWR, RD, AS, P6
method of selecting the pin states. In mode 7 (single-chip mode) port 6 is a generic input/output
port.
Pins in port 6 can drive one TTL load and a 30-pF capacitive load. They can also drive a
darlington transistor pair.
Rev. 3.00 Sep 27, 2006 page 280 of 872
REJ09B0325-0300
Port 6
Port 6
Overview
Port 6 pins
P6 /
P6 /
P6 /
P6 /
P6 /
P6 /
P6 /
6
5
4
3
2
1
0
LWR
HWR
RD
AS
BACK
BREQ
WAIT
Figure 9.6 Port 6 Pin Configuration
2
/BACK, P6
Modes 1 to 6
(expanded modes)
P6
P6
P6
2
1
0
(input/output)/
(input/output)/
(input/output)/
1
/BREQ, and P6
LWR
HWR
RD
AS
BACK
BREQ
WAIT
(output)
(output)
(output)
(output)
(output)
(input)
(input)
0
/WAIT. See table 9.11 for the
Mode 7
(single-chip mode)
P6
P6
P6
P6
P6
P6
P6
6
5
4
3
2
1
0
(input/output)
(input/output)
(input/output)
(input/output)
(input/output)
(input/output)
(input/output)
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