HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 269

IC H8 MCU FLASH 128K 100QFP

HD64F3048BF25

Manufacturer Part Number
HD64F3048BF25
Description
IC H8 MCU FLASH 128K 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3048BF25

Core Processor
H8/300H
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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8.4.8
Figure 8.13 shows an example of the timing of the basic DMAC bus cycle. This example shows a
word-size transfer from a 16-bit two-state access area to an 8-bit three-state access area. When the
DMAC gets the bus from the CPU, after one dead cycle (T
writes to the destination address. During these read and write operations the bus is not released
even if there is another bus request. DMAC cycles comply with bus controller settings in the same
way as CPU cycles.
Address
bus
RD
HWR
LWR
DMAC Bus Cycle
T
1
CPU cycle
T
2
Figure 8.13 DMA Transfer Bus Timing (Example)
T
1
T
2
T
d
T
Source
address
1
DMAC cycle (word transfer)
T
2
T
1
T
Destination address
2
Rev. 3.00 Sep 27, 2006 page 241 of 872
T
d
3
), it reads from the source address and
T
1
T
2
Section 8 DMA Controller
T
3
T
1
REJ09B0325-0300
T
CPU cycle
2
T
1
T
2

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