HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 616

• Manufacturer Part Number: HD64F3048BF25
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048BF25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 18 ROM (H8/3048F-ONE: Single Power Supply, H8/3048B Mask ROM Version)
18.5.2
Bit
Initial value
Read/Write
FLMCR2 is an 8-bit register used for flash memory operating mode control. FLMCR2 is
initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When
the on-chip flash memory is disabled, a read will return H'00.
Note: Bits 6 to 0 are reserved bits but are readable/writable.
Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on
flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-
protection state.
Bit 7:
FLER
0
1
Bits 6 to 0—Reserved: These bits are readable/writable.
Rev. 3.00 Sep 27, 2006 page 588 of 872
REJ09B0325-0300
Flash Memory Control Register 2 (FLMCR2)
Description
Flash memory is operating normally
Flash memory program/erase protection (error protection) is disabled
[Clearing condition]
Reset (RES pin or WDT reset) or hardware standby mode
An error occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting conditions]
FLER
When flash memory is read during programming/erasing (including a vector read
or instruction fetch, but excluding a read of the RAM area overlapping flash
memory space)
Immediately after the start of exception handling during programming/erasing
(excluding reset, illegal instruction, trap instruction, and division-by-zero exception
handling)
When a SLEEP instruction (including software standby) is executed during
programming/erasing
When the bus is released during programming/erasing
R
7
0
R/W
—
6
0
R/W
—
5
0
R/W
—
4
0
R/W
—
3
0
R/W
—
2
0
R/W
—
1
0
(Initial value)
R/W
—
0
0