HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 13

• Manufacturer Part Number: HD64F3048BF25
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048BF25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Item
13.3.3 Multiprocessor
Communication
Figure 13.11
Example of SCI
Transmit Operation
(8-Bit Data with
Multiprocessor Bit and
One Stop Bit)
13.3.4 Synchronous
Operation
Clock
14.2.3 Serial Mode
Register (SMR)
Bit 7—GSM Mode
(GM)
18.5.1 Flash Memory
Control Register 1
(FLMCR1)
Bit 1—Erase Bit (E)
Section 21 Electrical
Characteristics
Table 21.1 Electrical
Characteristics of
H8/3048 Group and
H8/3048B Group
Products
Page
495
500
521
587
653,
654
Revision (See Manual for Details)
Figure amended
TDRE
TEND
Description amended
An internal clock generated by the on-chip baud rate
generator or an external clock input from the SCK pin can be
selected by setting the C/A bit in SMR and the CKE1 and
CKE0 bits in SCR. See table 13.9.
Table amended
Note amended
Note: * Do not access flash memory while the E bit is set to 1.
Table amended
Bit 7: GM
0
1
Absolute
maximum
ratings
Flash
memory
charac-
teristics *
1
4
TXI
request
Start
bit
Description
Using the regular smart card interface mode
Using the GSM mode smart card interface mode
V
Item
0
PP
The TEND flag is set 12.5 etu after the beginning of the start bit
Clock output on/off control only
The TEND flag is set 11.0 etu after the beginning of the start bit
Clock output on/off and fixed-
(set by SCR)
pin rating
TXI interrupt handler
writes data in TDR and
clears TDRE flag to 0
D0
D1
1 frame
Data
D7
Rev. 3.00 Sep 27, 2006 page xi of xxvi
H8/3048
ZTAT
Yes
0/1
—
Multi-
processor
bit
H8/3048B Group
Stop
bit
TXI
request
1
high/fixed-low control
See table
21.11
H8/3048
Supply)
(Single
Start
bit
F-ONE
Power
0
—
D0
H8/3048B
D1
Mask
ROM
—
—
Data
D7
0/1
Multi-
processor
bit
TEI request
Stop
bit
1
(Initial value)
Idle (mark)
state
1