MMC2107CFCAG33 Freescale Semiconductor, MMC2107CFCAG33 Datasheet - Page 534

• Manufacturer Part Number: MMC2107CFCAG33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2107
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: Mcore
• Device Core: MCORE
• Device Core Size: 32b
• Frequency (max): 33MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 72
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 3.6/5.5V
• Operating Supply Voltage (min): 2.7/4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

JTAG Test Access Port and OnCE
Technical Data
534
21.13.4
21.13.5
21.13.6
21.14
21.14.1
21.14.2
21.14.3
21.14.3.1
21.14.3.2
21.14.3.3
21.14.3.4
21.14.3.5
21.14.3.6
21.14.3.7
21.14.4
21.14.4.1
21.14.4.2
21.14.4.3
21.14.5
21.14.6
21.14.6.1
21.14.6.2
21.14.7
21.14.7.1
21.14.7.2
21.14.8
21.14.8.1
21.14.8.2
21.14.9
21.14.9.1
21.14.9.2
21.14.9.3
21.14.9.4
21.14.10 Enabling OnCE Trace Mode . . . . . . . . . . . . . . . . . . . . . . 575
21.14.11 Enabling OnCE Memory Breakpoints . . . . . . . . . . . . . . . 576
21.14.12 Pipeline Information and Write-Back Bus Register . . . . . 576
21.14.12.1
21.14.12.2
Freescale Semiconductor, Inc.
For More Information On This Product,
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
JTAG Test Access Port and OnCE
Debug Mode Select (TMS). . . . . . . . . . . . . . . . . . . . . . . . 556
Test Reset (TRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
Debug Event (DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .557
OnCE Controller and Serial Interface. . . . . . . . . . . . . . . . 558
OnCE Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 559
OnCE Controller Registers. . . . . . . . . . . . . . . . . . . . . . . . 561
OnCE Decoder (ODEC) . . . . . . . . . . . . . . . . . . . . . . . . . . 570
Memory Breakpoint Logic . . . . . . . . . . . . . . . . . . . . . . . . 570
Breakpoint Address Mask Registers . . . . . . . . . . . . . . . . 571
OnCE Trace Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
Methods of Entering Debug Mode . . . . . . . . . . . . . . . . . . 574
Go to: www.freescale.com
Internal Debug Request Input (IDR) . . . . . . . . . . . . . . 559
CPU Debug Request (DBGRQ). . . . . . . . . . . . . . . . . . 560
CPU Debug Acknowledge (DBGACK). . . . . . . . . . . . . 560
CPU Breakpoint Request (BRKRQ). . . . . . . . . . . . . . . 560
CPU Address, Attributes (ADDR, ATTR) . . . . . . . . . . . 560
CPU Status (PSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . 560
OnCE Debug Output (DEBUG) . . . . . . . . . . . . . . . . . .560
OnCE Command Register . . . . . . . . . . . . . . . . . . . . . . 561
OnCE Control Register . . . . . . . . . . . . . . . . . . . . . . . . 564
OnCE Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 568
Memory Address Latch (MAL) . . . . . . . . . . . . . . . . . . .571
Breakpoint Address Base Registers . . . . . . . . . . . . . . 571
Breakpoint Address Comparators . . . . . . . . . . . . . . . . 572
Memory Breakpoint Counters . . . . . . . . . . . . . . . . . . . 572
OnCE Trace Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 573
Trace Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
Debug Request During RESET . . . . . . . . . . . . . . . . . . 574
Debug Request During Normal Activity . . . . . . . . . . . . 575
Debug Request During Stop, Doze, or Wait Mode . . . 575
Software Request During Normal Activity . . . . . . . . . . 575
Program Counter Register . . . . . . . . . . . . . . . . . . . . . . 577
Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
MMC2107 – Rev. 2.0
MOTOROLA