MMC2107CFCAG33 Freescale Semiconductor, MMC2107CFCAG33 Datasheet - Page 400

• Manufacturer Part Number: MMC2107CFCAG33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2107
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: Mcore
• Device Core: MCORE
• Device Core Size: 32b
• Frequency (max): 33MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 72
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 3.6/5.5V
• Operating Supply Voltage (min): 2.7/4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Queued Analog-to-Digital Converter (QADC)
Technical Data
400
18.8.6
18.8.6.1
18.8.6.2
18.8.7
18.8.8
18.8.8.1
18.8.8.2
18.8.8.3
18.9
18.9.1
18.9.2
18.9.2.1
18.9.2.2
18.9.2.3
18.9.3
18.9.3.1
18.9.3.2
18.9.3.3
18.9.3.4
18.9.3.5
18.9.3.6
18.9.3.7
18.9.3.8
18.9.3.9
18.10 Digital Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .450
18.10.1 Queue Priority Timing Examples. . . . . . . . . . . . . . . . . . . . 450
18.10.1.1
18.10.1.2
18.10.2 Boundary Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
18.10.3 Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
18.10.4 Disabled Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
18.10.5 Reserved Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
18.10.6 Single-Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
18.10.6.1
18.10.6.2
18.10.6.3
18.10.6.4
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427
Conversion Command Word Table . . . . . . . . . . . . . . . . . .437
Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .441
QADC Bus Accessing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
External Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
QADC Status Register 0 . . . . . . . . . . . . . . . . . . . . . . . . 427
QADC Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . 436
Right-Justified Unsigned Result Register. . . . . . . . . . . . 441
Left-Justified Signed Result Register . . . . . . . . . . . . . . . 442
Left-Justified Unsigned Result Register . . . . . . . . . . . . . 442
External Multiplexing Operation . . . . . . . . . . . . . . . . . . .443
Module Version Options. . . . . . . . . . . . . . . . . . . . . . . . . 444
External Multiplexed Address Configuration . . . . . . . . .446
Analog-to-Digital Converter Operation . . . . . . . . . . . . . .446
Conversion Cycle Times . . . . . . . . . . . . . . . . . . . . . . . . 446
Channel Decode and Multiplexer . . . . . . . . . . . . . . . . . . 448
Sample Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .448
Digital-to-Analog Converter (DAC) Array . . . . . . . . . . . . 449
Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Successive-Approximation Register . . . . . . . . . . . . . . . 449
State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .450
Queue Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .451
Queue Priority Schemes . . . . . . . . . . . . . . . . . . . . . . . . 453
Software-Initiated Single-Scan Mode. . . . . . . . . . . . . . . 468
External Trigger Single-Scan Mode . . . . . . . . . . . . . . . . 469
External Gated Single-Scan Mode. . . . . . . . . . . . . . . . . 470
Interval Timer Single-Scan Mode. . . . . . . . . . . . . . . . . . 470
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MMC2107 – Rev. 2.0
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