MMC2107CFCAG33 Freescale Semiconductor, MMC2107CFCAG33 Datasheet - Page 145

• Manufacturer Part Number: MMC2107CFCAG33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2107
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: Mcore
• Device Core: MCORE
• Device Core Size: 32b
• Frequency (max): 33MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 72
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 3.6/5.5V
• Operating Supply Voltage (min): 2.7/4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.4 Microarchitecture Summary
MMC2107 – Rev. 2.0
MOTOROLA
DATA CALCULATION
WRITEBACK BUS
SIGN EXT.
GENERAL-PURPOSE
REGISTER FILE
X PORT
32 BITS X 16
ADDER/LOGICAL PRIORITY ENCODER/
MUX
ZERO DETECT RESULT MUX
BARREL SHIFTER
REGISTER FILE
Figure 6-1. M•CORE Processor Block Diagram
ALTERNATE
32 BITS X 16
MULTIPLIER
Figure 6-1
The processor utilizes a 4-stage pipeline for instruction execution. The
instruction fetch, instruction decode/register file read, execute, and
register file writeback stages operate in an overlapped fashion, allowing
single clock instruction execution for most instructions.
The execution unit consists of a 32-bit arithmetic/logic unit, a 32-bit
barrel shifter, a find-first-one unit, result feed-forward hardware, and
miscellaneous support hardware for multiplication, division, and
multiple-register loads and stores.
DIVIDER
Freescale Semiconductor, Inc.
M•CORE M210 Central Processor Unit (CPU)
For More Information On This Product,
H/W ACCELERATOR INTERFACE BUS
Y PORT
MUX
is a block diagram of the M•CORE processor.
REGISTER FILE
Go to: www.freescale.com
SCALE
32 BITS X 13
CONTROL
IMMEDIATE
MUX
DATA
BUS
M•CORE M210 Central Processor Unit (CPU)
INCREMENT
ADDRESS GENERATION
INSTRUCTION PIPELINE
INSTRUCTION DECODE
PC
ADDRESS MUX
Microarchitecture Summary
BRANCH
ADDER
Technical Data
ADDRESS
BUS
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