MMC2107CFCAG33 Freescale Semiconductor, MMC2107CFCAG33 Datasheet - Page 33

• Manufacturer Part Number: MMC2107CFCAG33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2107
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: Mcore
• Device Core: MCORE
• Device Core Size: 32b
• Frequency (max): 33MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 72
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 3.6/5.5V
• Operating Supply Voltage (min): 2.7/4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MMC2107 – Rev. 2.0
MOTOROLA
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Freescale Semiconductor, Inc.
For More Information On This Product,
Start Bit Search Example 3 . . . . . . . . . . . . . . . . . . . . . . . . 360
Start Bit Search Example 4 . . . . . . . . . . . . . . . . . . . . . . . . 361
Start Bit Search Example 5 . . . . . . . . . . . . . . . . . . . . . . . . 361
Start Bit Search Example 6 . . . . . . . . . . . . . . . . . . . . . . . . 362
Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Single-Wire Operation (LOOPS = 1, RSRC = 1) . . . . . . . . 366
Loop Operation (LOOPS = 1, RSRC = 0) . . . . . . . . . . . . . 367
SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
SPI Control Register 1 (SPICR1) . . . . . . . . . . . . . . . . . . . . 376
SPI Control Register 2 (SPICR2) . . . . . . . . . . . . . . . . . . . . 378
SPI Baud Rate Register (SPIBR) . . . . . . . . . . . . . . . . . . . . 379
SPI Status Register (SPISR) . . . . . . . . . . . . . . . . . . . . . . .381
SPI Data Register (SPIDR) . . . . . . . . . . . . . . . . . . . . . . . . 382
SPI Pullup and Reduced Drive Register (SPIPURD) . . . . .383
SPI Port Data Register (SPIPORT) . . . . . . . . . . . . . . . . . .384
SPI Port Data Direction Register (SPIDDR). . . . . . . . . . . . 385
Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
SPI Clock Format 1 (CPHA = 1). . . . . . . . . . . . . . . . . . . . . 389
SPI Clock Format 0 (CPHA = 0). . . . . . . . . . . . . . . . . . . . . 391
Transmission Error Due to Master/Slave Clock Skew . . . .392
QADC Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
QADC Input and Output Signals . . . . . . . . . . . . . . . . . . . . 406
QADC Module Configuration Register (QADCMCR) . . . . .411
QADC Test Register (QADCTEST) . . . . . . . . . . . . . . . . . .412
QADC Port QA Data Register (PORTQA) . . . . . . . . . . . . . 413
QADC Port QB Data Register (PORTQB) . . . . . . . . . . . . . 413
QADC Port QA Data Direction Register (DDRQA). . . . . . . 415
QADC Control Register 0 (QACR0) . . . . . . . . . . . . . . . . . . 416
QADC Control Register 1 (QACR1) . . . . . . . . . . . . . . . . . . 419
QADC Control Register 2 (QACR2) . . . . . . . . . . . . . . . . . . 422
QADC Status Register 0 (QASR0) . . . . . . . . . . . . . . . . . . .427
Queue Status Transition. . . . . . . . . . . . . . . . . . . . . . . . . . . 435
QADC Status Register 1 (QASR1) . . . . . . . . . . . . . . . . . . .436
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