MMC2107CFCAG33 Freescale Semiconductor, MMC2107CFCAG33 Datasheet - Page 171

• Manufacturer Part Number: MMC2107CFCAG33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2107
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: Mcore
• Device Core: MCORE
• Device Core Size: 32b
• Frequency (max): 33MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 72
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 3.6/5.5V
• Operating Supply Voltage (min): 2.7/4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.8.4 Interrupt Configuration
7.8.4.1 M•CORE Processor Configuration
7.8.4.2 Interrupt Controller Configuration
MMC2107 – Rev. 2.0
MOTOROLA
After reset, all interrupts are disabled by default. To properly configure
the system to handle interrupt requests, configuration must be
performed at three levels:
Configure the M•CORE first, the interrupt controller second, and the
local interrupt sources last.
For fast interrupts, set the FIE[x] bit in FIER in the M•CORE processor.
For normal interrupts, set the NIE[x] bit. Both FIE and NIE are cleared at
reset. To allow long latency, multicycle instructions to be interrupted
before completion, set the IC bit.
VBR in the M•CORE processor defines the base address of the
exception vector table. If autovectors are to be used, then initialize the
INT and FINT autovectors (vector numbers 10 and 11, respectively). If
vectored interrupts are to be used, then initialize the vectored interrupts
(vector numbers 32–63 and/or 64–95). Whether 32 or 64 vectors are
required depends on whether the fast interrupts share vectors with the
normal interrupt sources based on the FVE bit in the interrupt controller
ICR.
For each vector number, create an interrupt service routine to service
the interrupt, clear the local interrupt flag, and return from the interrupt
routine.
By default, each interrupt source to the interrupt controller is assigned a
priority level of 0 and disabled. Each interrupt source can be
programmed to one of 32 priority levels and enabled as either a fast or
normal interrupt source. Also, the FVE and AE bits in ICR can be
programmed to select autovectored/vectored interrupts and also
determine if the fast interrupt vector number is to be separate from the
normal interrupt vector.
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Freescale Semiconductor, Inc.
For More Information On This Product,
M•CORE processor
Interrupt controller
Local interrupt sources
Go to: www.freescale.com
Interrupt Controller Module
Interrupt Controller Module
Functional Description
Technical Data
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