MMC2107CFCAG33 Freescale Semiconductor, MMC2107CFCAG33 Datasheet - Page 510

• Manufacturer Part Number: MMC2107CFCAG33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2107
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: Mcore
• Device Core: MCORE
• Device Core Size: 32b
• Frequency (max): 33MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 72
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 3.6/5.5V
• Operating Supply Voltage (min): 2.7/4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

External Bus Interface Module (EBI)
19.6 Enable Byte Pins (EB[3:0])
19.7 Bus Master Cycles
Technical Data
510
The enable byte pins (EB[3:0]) are configurable as byte enables for read
and write cycles, or as write enables for write cycles only. The default
function is byte enable unless there is an active chip-select match with
the WE bit set. In all external cycles when one or more EB pins are
asserted, the encoding corresponds to the external data pins to be used
for the transfer as outlined in
In this subsection, each EBI bus cycle type is defined in terms of actions
associated with a succession of internal states. These internal states are
only for reference and may not correspond to any implemented machine
states.
Read or write operations may require multiple bus cycles to complete
based on the operand size and target port size. Refer to
Transfer
assumed that only a single bus cycle is required for a transfer.
In the waveform diagrams
transfers are related to clock cycles, independent of the clock frequency.
The external bus states are also noted.
Freescale Semiconductor, Inc.
For More Information On This Product,
External Bus Interface Module (EBI)
for more information. In the discussion that follows, it is
Go to: www.freescale.com
Table 19-3. EB[3:0] Assertion Encoding
EB Pin
EB0
EB1
EB2
EB3
(Figure 19-3
Table
19-3.
through
External Data Pins
D[31:24]
D[23:16]
D[15:8]
D[7:0]
Figure
MMC2107 – Rev. 2.0
19-6), data
19.5 Operand
MOTOROLA