MMC2107CFCAG33 Freescale Semiconductor, MMC2107CFCAG33 Datasheet - Page 490

• Manufacturer Part Number: MMC2107CFCAG33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2107
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: Mcore
• Device Core: MCORE
• Device Core Size: 32b
• Frequency (max): 33MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 72
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 3.6/5.5V
• Operating Supply Voltage (min): 2.7/4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Queued Analog-to-Digital Converter (QADC)
18.11.4 Analog Supply Filtering and Grounding
Technical Data
490
Figure 18-48
scan with same assumptions in example 1 except:
When the gate closes and opens again, the conversions start with the
first CCW in Q1.
When the gate closes, the active conversion completes before the
queue goes idle.
When Q1 completes both the CF1 bit sets and the SSE bit clears.
A proposed amended definition for the PF bit in this mode, to reflect the
condition that a gate closing occurred before the queue completed, is
under consideration.
Figure 18-49
continuous scan with the same assumptions as in
At the end of Q1,the completion flag CF1 sets and the queue restarts. If
the queue starts a second time and completes, the trigger overrun flag
TOR1 sets.
Two important factors influencing performance in analog integrated
circuits are supply filtering and grounding. Generally, digital circuits use
bypass capacitors on every V
subsystems or submodules also. Equally important as bypassing is the
distribution of power and ground.
•
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
No pause bits set in any CCW
External trigger gated mode single scan for Q1
Single scan bit is set.
Go to: www.freescale.com
shows the timing for conversions in gated mode single
shows the timing for conversions in gated mode
DD
/V
SS
pin pair. This applies to analog
Figure
MMC2107 – Rev. 2.0
18-48.
MOTOROLA