DS80C390-QCR+ Maxim Integrated Products, DS80C390-QCR+ Datasheet - Page 53

IC MPU CAN DUAL HS 68-PLCC

DS80C390-QCR+

Manufacturer Part Number
DS80C390-QCR+
Description
IC MPU CAN DUAL HS 68-PLCC
Manufacturer
Maxim Integrated Products
Series
80Cr
Datasheet

Specifications of DS80C390-QCR+

Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SIO, UART/USART
Peripherals
Power-Fail Reset, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3.85 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-LCC, 68-PLCC
Processor Series
DS80C390
Core
8051
Data Bus Width
8 bit
Program Memory Size
4 KB
Data Ram Size
4 KB
Interface Type
CAN, IrDA
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
3.85 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
0 C
Package
68PLCC
Device Core
8051
Family Name
80C
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
REVISION HISTORY
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
M a x i m I n t e g r a t e d P r o d u c t s , 1 2 0 S a n G a b r i e l D r i v e , S u n n y v a l e , C A 9 4 0 8 6 4 0 8 - 7 3 7 - 7 6 0 0
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corp.
REVISION
062299
090799
110199
032904
022305
060805
110905
Initial preliminary release.
Clarifies that unused/unimplemented bits in the CAN MOVX SRAM read 0.
Corrected the t
Corrected multiplexed 2-cycle date memory CEO-3 read figure to show RD and WR inactive.
Corrected P5.2 and P5.3 pin descriptions.
Corrected description of sequence to activate the crystal frequency multiplier.
Corrected references to PQFP to read LQFP.
Added RSTOL timing information.
Official release (removed “preliminary” status).
Abs max soldering temp now references JEDEC standard.
AC and DC specifications updated to reflect final characterization data.
Clarified DC characteristics Note 6 concerning port 4 and 5.
Removed Figure 1. Typical I
Added t
Clarified that t
Removed t
Corrected PSEN trace in Figure 10 to not show assertion during MOVX write.
Corrected Table 3 to show unnecessary steps during 16/16 divide.
Supplied approximate oscillator-fail detection frequency.
Removed text references to Stop mode current.
Corrected location of PT2 in Table 14.
In Absolute Maximum Ratings section (page 2):
In DC Electrical Characteristics table (page 2):
Added lead-free part numbers to Ordering Information table.
Added new paragraph to page 33 stating “Software must ensure that the input value for the
normalize operation is not zero or the function will not complete. Compilers such as the one from
Keil Software have updated their libraries and compensate for this condition.”
Table 3: clarified text under “Normalize” function. Changed “Configure MCNTO register as
required.” to “Load MCNT0 with 00h.”
In AC Electrical Characteristics table (page 3):
Removed “A” from IPC/JEDEC J-STD-020A specification to support lead-free devices.
Changed V
Changed V
Changed V
Changed V
Changed V
Added Note 10
Added note to (now) Note 11 that AC timing is characterized and guaranteed by design but
is not production tested.
LLAX3
PXIZ
specification (identical to t
RLAZ
, t
MCS
PFW
PFW
RST
RST
IH2
PHAV
is held weak latch until overdriven by external memory.
MIN reference to 0.7 x V
time period table.
MIN to 3.85V from 3.95V
MAX to 4.35V from 4.3V
MIN to 4.10V from 4.20V
MAX to 4.60V from 4.55V
, t
PHWL
, and t
© 2005 Maxim Integrated Products \
CC
vs. Frequency.
PHRL
from nonmultiplexed address/data bus table.
LLAX2
53 of 53
DESCRIPTION
CC
).
from 0.7 x V
DS80C390 Dual CAN High-Speed Microprocessor
DD

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