DS80C390-QCR+ Maxim Integrated Products, DS80C390-QCR+ Datasheet - Page 49

• Manufacturer Part Number: DS80C390-QCR+
• Description: IC MPU CAN DUAL HS 68-PLCC
• Manufacturer: Maxim Integrated Products
• Series: 80Cr

Specifications of DS80C390-QCR+

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SIO, UART/USART
• Peripherals: Power-Fail Reset, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.85 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-LCC, 68-PLCC
• Processor Series: DS80C390
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Size: 4 KB
• Data Ram Size: 4 KB
• Interface Type: CAN, IrDA
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 3.85 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Package: 68PLCC
• Device Core: 8051
• Family Name: 80C
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

DS80C390 Dual CAN High-Speed Microprocessor
CAN INTERRUPTS
The DS80C390 supports three interrupts associated with the CAN controllers. One interrupt is dedicated to each
CAN controller, providing receive/transmit acknowledgments from each of its 15 message centers. The remaining
interrupt, the CAN bus activity interrupt, is used to detect CAN bus activity on the C0RX or C1RX pins.
The message center interrupts are enabled/disabled by individual ETI (transmit) and ERI (receive) enable bits in
the corresponding message control register (located in SFR memory) for each message center. All the message
center interrupts of each CAN module are ORed together into their respective CAN interrupt. The successful
transmission or receipt of a message sets the INTRQ bit in the corresponding message control register (located in
SFR memory). This bit can only be cleared through software. In addition, the global interrupt-enable bit (IE.7) and
the specific CAN interrupt-enable bit, EIE.6 (CAN0) or EIE.5 (CAN1), must be correctly set to acknowledge a
message center interrupt.
Interrupt assertion of error and status conditions associated with the CAN modules is controlled by the ERIE and
STIE bits located in the CAN control registers, C0C and C1C.
ARBITRATION AND MASKING
After a CAN module has ascertained that an incoming message is bit-error-free, the identification field of that
message is then compared against one or more arbitration values to determine if they will be loaded into a
message center. Each enabled message center (see the MSRDY bit in the CAN Message Control Register) is
tested in order from 1 to 15. The first message center to successfully pass the test receives the incoming message
and ends the testing. Using masking registers allows the use of more complex identification schemes, as tests can
be made based on bit patterns rather than an exact match between all bits in the identification field and arbitration
values. Each CAN processor also incorporates a set of five masks to allow messages with different IDs to be
grouped and successfully loaded into a message center. Note that some of these masks are optional as per the
bits shown in the Arbitration/Masking Feature Summary table
(Table
14).
There are several possible arbitration tests, varying according to which message center is involved. If all the
enabled tests succeed, the message is loaded into the respective message center. The most basic test, performed
on all messages, compares either 11 (CAN 2.0A) or 29 (CAN 2.0B) bits of the identification field to the appropriate
arbitration register, based on the EX/ST bit in the CAN 0/1 format register. The MEME bit (C0MxF.1 or C1MxF.1)
controls whether the arbitration and ID registers are compared directly or through a mask register. A special set of
arbitration registers dedicated to message center 15 allows added flexibility in filtering this location.
If desired, further arbitration can be performed by comparing the first two bytes of the data field in each message
against two 8-bit media arbitration register bytes. The MDME bit in the CAN message center format registers
(C0MxF.0 or C1MxF.0) either disables (MDME = 0) arbitration, or enables (MDME = 1) arbitration using the media
ID mask registers 0–1.
If the 11-bit or 29-bit arbitration and the optional media-byte arbitration are successful, the message is loaded into
the respective message center. The format register also allows the microcontroller to program each message
center to function in a receive or transmit mode through the T/R bit, and to use from 0 to 8 data bytes within the
data field of a message. Note that message center 15 can only be used in a receive mode. To avoid a priority
inversion, the DS80C390 CAN processors are configured to reload the transmit buffer with the message of the
highest priority (lowest message center number) whenever an arbitration is lost or an error condition occurs.
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