DS80C390-QCR+ Maxim Integrated Products, DS80C390-QCR+ Datasheet - Page 40

• Manufacturer Part Number: DS80C390-QCR+
• Description: IC MPU CAN DUAL HS 68-PLCC
• Manufacturer: Maxim Integrated Products
• Series: 80Cr

Specifications of DS80C390-QCR+

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SIO, UART/USART
• Peripherals: Power-Fail Reset, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.85 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-LCC, 68-PLCC
• Processor Series: DS80C390
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Size: 4 KB
• Data Ram Size: 4 KB
• Interface Type: CAN, IrDA
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 3.85 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Package: 68PLCC
• Device Core: 8051
• Family Name: 80C
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

DS80C390 Dual CAN High-Speed Microprocessor
POWER MANAGEMENT MODE (PMM) AND SWITCHBACK
Power consumption in PMM is less than in idle mode, and approximately one quarter of that consumed in divide-
by-four mode. While PMM and Idle modes leave the power-hungry internal timers running, PMM runs all clocked
functions such as timers at the rate of crystal divided by 1024, rather than crystal divided by 4. Even though
instruction execution continues in PMM (albeit at a reduced speed), it still consumes less power than idle mode. As
a result there is little reason to use idle mode in new designs.
When enabled, the switchback feature allows serial ports and interrupts to automatically switch back from divide by
1024 (PMM) to divide-by-4 (standard speed) operation. This feature makes it very convenient to use the PMM in
real-time applications. Software can simply set the CD1 and CD0 clock control bits to the 4 clocks-per-cycle mode
to exit PMM. However, the microcontroller provides hardware alternatives for automatic Switchback to standard
speed (divide-by-4) operation.
Setting the SFR bit SWB (PMR.5) to 1 enables the switchback feature. Once it is enabled, and when PMM is
selected, two possible events can cause an automatic switchback to divide-by-4 mode. First, if an interrupt occurs
and is acknowledged, the system clock reverts from PMM to divide-by-4 mode. For example, if INT0 is enabled and
the CPU is not servicing a higher priority interrupt, then switchback occurs on INT0. However, if INT0 is not
enabled or the CPU is servicing a higher priority interrupt, then activity on INT0 does not cause switchback to
occur.
A switchback can also occur when an enabled UART detects the start bit indicating the beginning of an incoming
serial character or when the SBUF register is loaded initiating a serial transmission. Note that a serial character’s
start bit does not generate an interrupt. The interrupt occurs only on reception of a complete serial word. The
automatic switchback on detection of a start bit allows timer hardware to return to divide-by-4 operation (and the
correct baud rate) in time for a proper serial reception or transmission. So with switchback enabled and a serial port
enabled, the automatic switch to divide-by-4 operation occurs in time to receive or transmit a complete serial
character as if nothing special had happened.
STATUS
The status register (STATUS;C5h) provides information about interrupt and serial port activity to assist in
determining if it is possible to enter PMM. The microprocessor supports three levels of interrupt priority: power-fail,
high, and low. The PIP (power-fail priority interrupt status; STATUS.7), HIP (high-priority interrupt status;
STATUS.6), and LIP (low-priority interrupt status; STATUS.5) status bits, when set to logic 1, indicate the
corresponding level is in service.
Software should not rely on a lower-priority level interrupt source to remove PMM (switchback) when a higher level
is in service. Check the current priority service level before entering PMM. If the current service level locks out a
desired switchback source, then it would be advisable to wait until this condition clears before entering PMM.
Alternately, software can prevent an undesired exit from PMM by intentionally entering a low priority interrupt
service level before entering PMM. This will prevent other low priority interrupts from causing a switchback.
Entering PMM during an ongoing serial port transmission or reception can corrupt the serial port activity. To
prevent this, a hardware lockout feature ignores changes to the clock divisor bits while the serial ports are active.
Serial port activity can be monitored via the serial port activity bits located in the status register.
IDLE MODE
Setting the IDLE bit (PCON.0) invokes the idle mode. Idle leaves internal clocks, serial ports, and timers running.
Power consumption drops because memory is not being accessed and instructions are not being executed. Since
clocks are running, the idle power consumption is a function of crystal frequency. It should be approximately one-
half of the operational power at a given frequency. The CPU can exit idle mode with any interrupt or a reset.
Because PMM consumes less power than idle mode, as well as leaving timers and CPU operating, idle mode is no
longer recommended for new designs, and is included for backward software compatibility only.
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