DS80C390-QCR+ Maxim Integrated Products, DS80C390-QCR+ Datasheet - Page 41

• Manufacturer Part Number: DS80C390-QCR+
• Description: IC MPU CAN DUAL HS 68-PLCC
• Manufacturer: Maxim Integrated Products
• Series: 80Cr

Specifications of DS80C390-QCR+

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SIO, UART/USART
• Peripherals: Power-Fail Reset, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.85 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-LCC, 68-PLCC
• Processor Series: DS80C390
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Size: 4 KB
• Data Ram Size: 4 KB
• Interface Type: CAN, IrDA
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 3.85 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Package: 68PLCC
• Device Core: 8051
• Family Name: 80C
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

DS80C390 Dual CAN High-Speed Microprocessor
STOP MODE
Setting the STOP bit of the power control register (PCON.1) invokes stop mode. Stop mode is the lowest power
state (besides power off) since it turns off all internal clocking. All processor operation ceases at the end of the
instruction that sets the STOP bit. The CPU can exit stop mode via an external interrupt, if enabled, or a reset
condition. Internally generated interrupts (timer, serial port, watchdog) cannot cause an exit from stop mode
because internal clocks are not active in stop mode.
BANDGAP SELECT
The DS80C390 provides two enhancements to stop mode. As described below, the device provides a band-gap
reference to determine power-fail interrupt and reset thresholds. The bandgap select bit, BGS (RCON.0), controls
the bandgap reference. Setting BGS to 1 keeps the bandgap reference enabled during stop mode. The default or
reset condition of the bit is logic 0, which disables the bandgap during stop mode. This bit has no control of the
reference during full power, PMM, or idle modes.
With the bandgap reference enabled, the power-fail reset and interrupt are valid means for leaving stop mode. This
allows software to detect and compensate for a power-supply sag or brownout, even when in stop mode. In stop
mode with the bandgap enabled, I
is higher compared to with the bandgap disabled. If a user does not require a
CC
power-fail reset or interrupt while in stop mode, the bandgap can remain disabled. Only the most power-sensitive
applications should disable the bandgap reference in stop mode, as this results in an uncontrolled power-down
condition.
RING OSCILLATOR
The second enhancement to Stop mode reduces power consumption and allows the device to restart instantly
when exiting stop mode. The ring oscillator is an internal clock that can optionally provide the clock source to the
microcontroller when exiting stop mode in response to an interrupt.
During stop mode the crystal oscillator is halted to maximize power savings. Typically, 4ms to 10ms is required for
an external crystal to begin oscillating again once the device receives the exit stimulus. The ring oscillator, by
contrast, is a free-running digital oscillator that has no startup delay. Setting the ring oscillator select bit, RGSL
(EXIF.1), enables the ring oscillator feature. If enabled, the microcontroller uses the ring oscillator as the clock
source to exit stop mode, resuming operation in less than 100ns. After 65,536 oscillations of the external clock
source (not the ring oscillator), the device clears the ring-oscillator-mode bit, RGMD (EXIF.2), to indicate that the
device has switched from the ring oscillator to the external clock source.
The ring oscillator runs at approximately 10MHz but varies over temperature and voltage. As a result, no serial
communication or precision timing should be attempted while running from the ring oscillator since the operating
frequency is not precise. The default state exits stop mode without using the ring oscillator.
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