DF2378BVFQ35WV Renesas Electronics America, DF2378BVFQ35WV Datasheet - Page 839

• Manufacturer Part Number: DF2378BVFQ35WV
• Description: IC H8S/2378 MCU FLASH 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378BVFQ35WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 35MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• For Use With: EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

An I
item:
1. For the masked ROM version, W is added to the model name of the product that uses optional
This LSI has a two-channel I
The I
(inter-IC bus) interface (Rev. 03) standard and fast mode functions. The register configuration that
controls the I
Figure 16.1 shows a block diagram of the I
Figure 16.2 shows an example of I/O pin connections to external circuits.
16.1
• Continuous transmission/reception
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Bit synchronization/wait function
• Six interrupt sources
• Direct bus drive
IFIIC40A_010020020400
functions.
For example: HD6432375WFQ
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically
If transmission/reception is not yet possible, set the SCL to low until preparations are
completed.
Transmit-data-empty (including slave-address match), transmit-end, receive-data-full
(including slave-address match), arbitration lost, NACK detection, and stop condition
detection
Two pins, SCL and SDA pins function as NMOS open-drain outputs.
2
C bus interface is an option. When using the optional functions, take notice of the following
2
C bus interface conforms to and provides a subset of the NXP Semiconductors I
Features
Section 16 I
2
C bus differs partly from the NXP Semiconductors configuration, however.
2
C bus interface.
2
C Bus Interface 2 (IIC2) (Option)
2
C bus interface 2.
Section 16 I
Rev.7.00 Mar. 18, 2009 page 771 of 1136
2
C Bus Interface 2 (IIC2) (Option)
REJ09B0109-0700
2
C bus